• Transactions of the Korean Society of Mechanical Engineers B
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• v.35 no.11
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• pp.1127-1131
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• 2011

We report on a pumpless cell culture chip in which a constant medium perfusion rate is maintained by balanced droplet dispensing. Previous chips had a decreasing perfusion rate due to the decreasing hydraulic-head difference ${\Delta}h$ between the inlet and drain. However, the present chip maintains a constant medium perfusion rate due to the constant ${\Delta}h$ between the inlet and drain maintained by balanced droplet dispensing. The perfusion rate Q was measured to be 0.1-$0.3{\mu}l$/min with a maximum deviation and error of 9.96% and 6.92%, respectively. In the perfusion culture (Q = 0.1-$0.3{\mu}l$/min), the maximum growth-rate of H358 cells was measured to be $57.8%{\pm}21.1%$ per day, which is 1.9 times higher than that of a static culture. The perfusion culture also resulted in higher cell viability than a static culture. The present chip offers a favorable environment with a high growth-rate and viability and thus has potential for use in the integrated cell culture system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.549-557
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• 2012

In this paper an on-chip photo energy harvesting system with MPPT(Maximum Power Point Tracking) control is proposed. The ISC(Integrated Solar Cell) is implemented using p-diff/n-well diodes available in CMOS processes. MPPT control is implemented using the linear relationship between the open-circuit voltage of a PV(Photovoltaic) cell and its MPP(Maximum Power Point) voltage such that a small pilot PV cell can track the MPP of a main PV cell in real time. Simulation results show that the designed circuit with the MPPT control delivers the MPP voltage to load even though the load is heavy such that the load circuit can operate properly. The proposed circuit is designed in 0.18um CMOS process. The designed main PV cell and pilot PV cell occupy $8mm^2$ and $0.4mm^2$ respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.397-404
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• 2012

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.

• Journal of electromagnetic engineering and science
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• v.14 no.3
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• pp.314-316
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• 2014

This letter presents two types of metamaterial-inspired absorbers adopting resistive trumpet structures at the X band. The unit cell of the first type is composed of a trumpet-shaped resonator loading a chip resistor, a metallic back plane, and a FR4 (${\varepsilon}_r=4.4-j0.02$) substrate between them (single-layer). The absorption rate is 99.5% at 13.3 GHz. The full width at half maximum (FWHM) is 95 % at 11.2 GHz (from 5.9 to 16.5 GHz). The size of unit cell is $5.6{\times}5.6{\times}2.4mm^3$. The second type has been optimized with a $7{\Omega}$/square uniform resistive coating, removing the chip resistors but leading to results comparable to the first type. The proposed absorbers are almost insensitive to polarizations of incident waves due to symmetric geometry.

• Proceedings of the PSK Conference
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• 2002.10a
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• pp.291.2-291.2
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• 2002

For the safety evaluation of adenovirus-mediated gene therapy. we have investigated gene and protein expression after transduction of adenoviral vector (Ad5CMV-p16) which contains tumor suppressor gene. p161NK4$\alpha$ in human non-small cell lung cancer (A549) cells. We compared the differential gene expression level in the A549 cells treated with Ad5CMV (null type) and Ad5CMV-p16 virus. respectively. by using cDNA membrane chip and oligonucleotide chip. (omitted)

• Electronics and Telecommunications Trends
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• v.38 no.1
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• pp.46-54
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• 2023

The announcement of the US Environmental Protection Agency that it will stop conducting or funding experimental studies on mammals by 2035 should prioritize ongoing efforts to develop and use alternative toxicity screening methods to animal testing. Toxicity screening is likely to be further developed considering the combination of human-induced pluripotent-stem-cell-derived organ-on-a-chip and multielectrode array (MEA) technologies. We briefly review the current status of MEA technology and MEA-based neuropharmacological drug screening using various cellular model systems. Highlighting the coronavirus disease pandemic, we shortly comment on the importance of early prediction of toxicity by applying artificial intelligence to the development of rapid screening methods.

• Journal of electromagnetic engineering and science
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• v.5 no.2
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• pp.92-96
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• 2005

This paper presents a novel microwave oscillator incorporating a simple microstrip ring type resonant cell as its terminating resonance component. Reduced chip size, higher dc-ac power efficiency, superior harmonic characteristics can be achieved from the introduction of a compact microstrip ring resonator cell. The oscillator provides a second harmonic suppression of 26.51 dB and the output power of 2.046 dBm at 2.11 GHz.

• 전기의세계
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• v.38 no.4
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• pp.24-35
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• 1989

최근 DRAM 시장을 주도하고 잇는 일본의 유수업체의 DRAM cell의 면적과 대비한 축전용량과의 관계로 한눈에 알 수 있다. 1M DRAM급에서 얻었던 Cs값을 확보하면서 Chip Size를 줄이기 위해서는 Cell Size가 축소 되어야 하며 이에 따른 Active Region의 감소를 만회하기 위해서는 3차원 구조를 가지는 Trench나 Stacked cell의 등장이 불가피하게 된것이다. 따라서, 본고에서는 추후로 기억소자의 고집적화에 따라 필수적으로 요구되는 이러한 3차원 Capacitor형성기술의 특징을 알아보고 그 문제점에 대해 살펴보고자 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.