• Title/Summary/Keyword: Cell-chip

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Analysis of read speed latency in 6T-SRAM cell using multi-layered graphene nanoribbon and cu based nano-interconnects for high performance memory circuit design

  • Sandip, Bhattacharya;Mohammed Imran Hussain;John Ajayan;Shubham Tayal;Louis Maria Irudaya Leo Joseph;Sreedhar Kollem;Usha Desai;Syed Musthak Ahmed;Ravichander Janapati
    • ETRI Journal
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    • v.45 no.5
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    • pp.910-921
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    • 2023
  • In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperaturedependent Cu and multilayered graphene nanoribbon (MLGNR)-based nanointerconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 ㎛ to 100 ㎛), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.

In situ analysis of capturing dynamics of magnetic nanoparticles in a microfluidic system

  • Munir, Ahsan;Zhu, Zanzan;Wang, Jianlong;Zhou, H. Susan
    • Smart Structures and Systems
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    • v.12 no.1
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    • pp.1-22
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    • 2013
  • Magnetic nanoparticle based bioseparation in microfluidics is a multiphysics phenomenon that involves interplay of various parameters. The ability to understand the dynamics of these parameters is a prerequisite for designing and developing more efficient magnetic cell/bio-particle separation systems. Therefore, in this work proof-of-concept experiments are combined with advanced numerical simulation to design and optimize the capturing process of magnetic nanoparticles responsible for efficient microfluidic bioseparation. A low cost generic microfluidic platform was developed using a novel micromolding method that can be done without a clean room techniques and at much lower cost and time. Parametric analysis using both experiments and theoretical predictions were performed. It was found that flow rate and magnetic field strength greatly influence the transport of magnetic nanoparticles in the microchannel and control the capturing efficiency. The results from mathematical model agree very well with experiments. The model further demonstrated that a 12% increase in capturing efficiency can be achieved by introducing of iron-grooved bar in the microfluidic setup that resulted in increase in magnetic field gradient. The numerical simulations were helpful in testing and optimizing key design parameters. Overall, this work demonstrated that a simple low cost experimental proof-of-concept setup can be synchronized with advanced numerical simulation not only to enhance the functional performance of magneto-fluidic capturing systems but also to efficiently design and develop microfluidic bioseparation systems for biomedical applications.

Analysis of gene expression during odontogenic differentiation of cultured human dental pulp cells

  • Seo, Min-Seock;Hwang, Kyung-Gyun;Kim, Hyong-Bum;Baek, Seung-Ho
    • Restorative Dentistry and Endodontics
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    • v.37 no.3
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    • pp.142-148
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    • 2012
  • Objectives: We analyzed gene-expression profiles after 14 day odontogenic induction of human dental pulp cells (DPCs) using a DNA microarray and sought candidate genes possibly associated with mineralization. Materials and Methods: Induced human dental pulp cells were obtained by culturing DPCs in odontogenic induction medium (OM) for 14 day. Cells exposed to normal culture medium were used as controls. Total RNA was extracted from cells and analyzed by microarray analysis and the key results were confirmed selectively by reverse-transcriptase polymerase chain reaction (RT-PCR). We also performed a gene set enrichment analysis (GSEA) of the microarray data. Results: Six hundred and five genes among the 47,320 probes on the BeadChip differed by a factor of more than two-fold in the induced cells. Of these, 217 genes were upregulated, and 388 were down-regulated. GSEA revealed that in the induced cells, genes implicated in Apoptosis and Signaling by wingless MMTV integration (Wnt) were significantly upregulated. Conclusions: Genes implicated in Apoptosis and Signaling by Wnt are highly connected to the differentiation of dental pulp cells into odontoblast.

Design and FPGA Implementation of Scalar Multiplication for A CryptoProcessor based on ECC(Elliptic Curve Cryptographics) (ECC(Elliptic Curve Crptographics) 기반의 암호프로세서를 위한 스칼라 곱셈기의 FPGA 구현)

  • Hwang Jeong-Tae;Kim Young-Chul
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.529-532
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    • 2004
  • The ECC(Elliptic Curve Cryptogrphics), one of the representative Public Key encryption algorithms, is used in Digital Signature, Encryption, Decryption and Key exchange etc. The key operation of an Elliptic curve cryptosystem is a scalar multiplication, hence the design of a scalar multiplier is the core of this paper. Although an Integer operation is computed in infinite field, the scalar multiplication is computed in finite field through adding points on Elliptic curve. In this paper, we implemented scalar multiplier in Elliptic curve based on the finite field GF($2^{163}$). And we verified it on the Embedded digital system using Xilinx FPGA connected to an EISC MCU. If my design is made as a chip, the performance of scalar multiplier applied to Samsung $0.35 {\mu}m$ Phantom Cell Library is expected to process at the rate of 8kbps and satisfy to make up an encryption processor for the Embedded digital doorphone.

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Clinical Applicability of Multi-Tumor Marker Protein Chips for Diagnosing Ovarian Cancer

  • Bian, Jing;Li, Bo;Kou, Xian-Juan;Wang, Xu-Na;Sun, Xiao-Xu;Ming, Liang
    • Asian Pacific Journal of Cancer Prevention
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    • v.15 no.19
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    • pp.8409-8411
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    • 2014
  • Purpose: To assess the value of multi-tumor marker protein chips in the diagnosis and treatment of ovarian cancer. Materials and Methods: Twelve tumor markers (CA19-9, NSE, CEA, CA242, CK19, ${\beta}$-HCG, AFP, SCC, c-PSA, CA125, CA724 and CA15-3) were detected by protein biochip in 220 patients with ovarian carcinomas, 205 with benign ovarian tumors and 200 healthy subjects. Results: The positivity rate was obviously higher in ovarian cancer (77.7%), than that in the benign cases (26.3%, p<0.01) and healthy subjects (4.5%, p<0.01). Serum levels of tumor markers were furthermore significantly higher in cases with lymph node metastasis (86.8%) than those without metastasis (44.7%), p<0.01. Conclusions: Multi-tumor marker protein chips provide important assistance in the diagnosis and treatment evaluation in ovarian cancers.

Design of High Performance Buffer Manager for an Input-Queued Switch (고성능 입력큐 스위치를 위한 버퍼관리기의 설계)

  • GaB Joong Jeong;Lee, Bhum-Cheol
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2003.05a
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    • pp.394-397
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    • 2003
  • In this paper, we describe the implementation of high performance buffer manager that is used in an advanced input-queued switch fabric. The designed buffer manager provides wire-speed cell/packet routing with low cost and tolerates the transmission pipeline latency of request and grant data. The buffer manager is implemented in a FPGA chip and supports the speed of OC-48c, 2.5Gbps per port.

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Development of Superconductive Arithmetic and Logic Devices (초전도 논리연산자의 개발)

  • Kang J. H
    • Progress in Superconductivity
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    • v.6 no.1
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    • pp.7-12
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    • 2004
  • Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

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A Low Power Phase-Change Random Access Memory Using A Selective Data Write Scheme (선택적 데이터 쓰기 기법을 이용한 저전력 상변환 메모리)

  • Yang, Byung-Do
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.1
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    • pp.45-50
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    • 2007
  • This paper proposes a low power selective data write (SDW) scheme for a phase-change random access memory (PRAM). The PRAM consumes large write power because large write currents are required during long time. At first, the SDW scheme reads a stored data during write operation. And then, it writes an input data only when the input and stored data are different. Therefore, it can reduce the write power consumption to a half. The 1K-bit PRAM test chip with $128{\times}8bits$ is implemented with a $0.8{\mu}m$ CMOS technology with a $0.8{\mu}m$ GST cell.

A Study on the Design of Water Pollution Alarm System using Solar Cell (솔라셀을 적용한 수질오염 경보 시스템의 설계에 관한 연구)

  • Yoon, Seok-Am;Choi, Jang-Gyun;Yoon, Hyung-Sang;Kim, Min;Lee, Gi-Je;Cha, In-Su
    • Proceedings of the KIPE Conference
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    • 1999.07a
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    • pp.569-572
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    • 1999
  • As the industry has been growing rapidly, the problem of environmental pollution has been on the rise seriously. In this paper, we used solar cells at the power supply unit of the equipment, which has been sold at present, for measuring the quality of water in order to complement the problem. Also, to get rid of the inconvenience that the examiners must go to the job site, check and collect the polluted water we set the goal at designing the water pollution alarm system which measures the quality of water automatically using one-chip microprocessor and materializing the program.

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Implementation of Quad-Band p-HEMT SP6T Switch for Handset Applications (개인 휴대통신용 4중대역 p-HEMT SR6T 스위치 구현)

  • Shin, One-Chul;Jeong, In-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.1
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    • pp.97-101
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    • 2011
  • Quad band p-HEMT SP6T switch for handset applications was developed. To achieve the low insertion loss and high isolation, trade-off between "On" state and "Off" state was considered by optimization of unit cell. Especially, in case isolation between transmit port and receive port, it was achieved by large capacitors and miniaturization of chip size was achieved by common voltage control and ground using back via process. Designed SP6T switch has size of $950um{\times}100um$ and take into consideration the gate recess error, excellent loss and isolation was confirmed in operating frequency.