• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• Microbiology and Biotechnology Letters
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• v.14 no.2
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• pp.199-203
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• 1986

A tubular tormentor was prepared by packing the wood chips and pumping the yeast solution of Saccharomyces formosensis in a tubular column. Investigations to characterize the ethanol fermentation in the immobilized cell tubular fermentor and to compare such a fermentors with other type fermentors were undertaken. Ethanol productivity of 24.4g EtOH/$\ell$.hr has been obtained from glucose substrate. This productivity is higher or compared favourably with that reported in immobilized bio-reactors.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.15-24
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• 1998

This paper proposes a new template matching algorithm and its chip design. The CC and SAD algorithms require the massive amount of computation. Hence, several algorithms using quantization schemes have been proposed to reduce the amount of computation and its hardware cost. the proposed algorithm called the EMPPM improves at least 22% of the noise margin compared with the MPPM algorithm. In addition, the proposed architecture can reduce the gate count by more than 60% of that used in the SAD algorithm without usig quantization schemes and 28% of the MPPM algorithm. The VHDL models have been simulated by using the CADANCETEX>$^{TM}$ and logic synthesis has been performed by using the SYNOPSYSTEX>$^{TM}$ with $0.6\mu\textrm{m}$ SOG(sea-of-gate) cell library. The implemented chip consists of 35,829 gates, operates at 100 MHz (worst case 53 MHz) and performs the template maching with the speed of 200 Mpixels/sec.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• BioChip Journal
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• v.12 no.4
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• pp.257-267
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• 2018

Inertial microfluidics has attracted significant attention in recent years due to its superior benefits of high throughput, precise control, simplicity, and low cost. Many inertial microfluidic applications have been demonstrated for physiological sample processing, clinical diagnostics, and environmental monitoring and cleanup. In this review, we discuss the fundamental mechanisms and principles of inertial migration and Dean flow, which are the basis of inertial microfluidics, and provide basic scaling laws for designing the inertial microfluidic devices. This will allow end-users with diverse backgrounds to more easily take advantage of the inertial microfluidic technologies in a wide range of applications. A variety of recent applications are also classified according to the structure of the microchannel: straight channels and curved channels. Finally, several future perspectives of employing fluid inertia in microfluidic-based cell sorting are discussed. Inertial microfluidics is still expected to be promising in the near future with more novel designs using various shapes of cross section, sheath flows with different viscosities, or technologies that target micron and submicron bioparticles.

• Journal of the Korean Society of Visualization
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• v.18 no.3
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• pp.84-89
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• 2020

Cancer cells secrete angiogenic factors, and nearby vasculatures make new blood vessels essential for cancer development and metastasis in response to these soluble factors. Many efforts have been made to elucidate cancer-endothelial cell interactions in vitro. However, not much is known due to the lack of a suitable co-culture platform. Here, we introduce a 3D printing-based microfluidic system that mimics the in vivo-like cancer-endothelial cell interactions. The tumoroids and endothelial cells are co-cultured, physically separated by porous fibrin gel, allowing communication between two cell types through soluble factors. Using this microfluidic system, we were able to visualize new vessel formation induced by tumoroids of different origins, including liver, breast, and ovary. We confirmed that the ovarian tumoroids most induced angiogenesis while the other two cancer types suppressed it. Utilization of the proposed co-culture platform will help the researchers unveil the underlying mechanisms of the dynamic interplay between tumor and angiogenesis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.261-267
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• 2001

This paper presents the architecture of multiple-queue manager for input-queued switch, which has arbitration latency, and the design of the chip. The proposed architecture of multiple-queue manager provides wire-speed routing with a pipelined buffer management, and the tolerance of requests and grants data transmission latency between the input queue manager and central arbiter using a new request control method, which is based on a high-speed shifter. The multiple-input-queue manager has been implemented in a field programmable gate array chip, which provides OC-48c port speed. It enhances the maximum throughput of the input queuing switch up to 98.6% with 128-cell shared input buffer in 16$\times$16 switch size.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.129-134
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• 2020

Moisture infiltration inside the solar cell module, filling of EVA sheet, melting of the frame seal, and deterioration of power generation performance in the module one year after installation are occurring. Whitening phenomenon, electrode corrosion phenomenon, and dielectric breakdown phenomenon are appearing in solar cell module installed in Korea before 5-7 years, leading to deterioration of power generation performance, and big problems for long-term reliability and long life technology are emerging. Therefore, in order to solve these problems, the development of a micro inverter (MiCrco Inverter Converter, MiC) including the function of securing the durability of the solar cell module and monitoring the aging progress and the solar cell based on the monitoring data from the MiC smart monitoring programs have been proposed to determine the aging of modules. In addition, in order to become a highly efficient solar smart monitoring system through systematic operation management through IT convergence with MiC that has enhanced monitoring function of solar cell module, SoC(System On Chip) in micro inverter is the environment for solar cell module. There is a demand for functions that can detect information in a complex manner and perform communication and control when necessary. Based on these requirements, this paper aims to develop SoC-based low-cost MiC smart photovoltaic system technology.