• 한국컴퓨터산업학회논문지
• /
• 제6권5호
• /
• pp.757-766
• /
• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• 한국전기전자재료학회논문지
• /
• 제19권4호
• /
• pp.314-321
• /
• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• 마이크로전자및패키징학회지
• /
• 제24권3호
• /
• pp.7-11
• /
• 2017

본 논문은 3차원 낸드 플래쉬 기억 소자에 적용을 위해 소노스(SONOS) 형태로 기억 저장 절연막을 채용하고 채널로 폴리실리콘을 사용한 박막형 트랜지스터에 대해 연구하였다. 셀의 source/drain에는 불순물을 주입 하지 않았고, 셀 양 끝단에는 선택 트랜지스터를 배치하였다. 셀의 채널과 선택 트랜지스터의 source/drain 불순물 농도 변화에 대한 평가를 진행하여 공정 최적화를 하였다. 선택 트랜지스터의 농도 증가 시 채널 전류의 상승 및 삭제특성이 개선됨을 확인 하였는데 이는 GIDL에 의한 홀 생성이 증가하였기 때문이다. 최적화된 공정 변수에 대해 삭제와 쓰기 후 문턱전압의 프로그램 윈도우는 대략 2.5V를 얻었다. 터널 산화막 공정 온도에 대한 평가 결과 온도 증가 시 swing 및 신뢰성 항목인 bake 결과가 개선됨을 확인하였다.

• 전기전자학회논문지
• /
• 제11권1호통권20호
• /
• pp.69-76
• /
• 2007

본 논문에서는 CMOS 공정기반의 BiCMOS LVDS 구동기를 설계하여 고속 I/O 인터페이스에 적용하고자 한다. 칩 면적을 줄이고 LVDS 구동기의 감내성을 향상시키기 위해 lateral 바이폴라 트랜지스터를 설계하여 LVDS 구동기의 바이폴라 스위칭으로 대체하였다. 설계된 바이폴라 트랜지스터는 20가량의 전류이득을 지니며, 설계된 LVDS 드라이버 셀 면적은 $0.01mm^2$로 설계되었다. 설계된 LVDS 드라이버는 1.8V의 전원 전압에서 최대 2.8Gb/s의 데이터 전송속도를 가진다. 추가적으로 ESD 현상을 보호하기 위해 새로운 구조의 ESD 보호 소자를 설계하였다. 이는 SCR구조에서 PMOS, NMOS의 턴-온 특성을 이용 낮은 트리거링 전압과 래치 업 현상을 최소화 시킬 수 있다. 시뮬레이션 결과 2.2V의 트리거링 전압과 1.1V의 홀딩 전압을 확인할 수 있었다.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
• /
• pp.427-427
• /
• 2012

Ferroelectric-gate field effect transistor based memory using a nanowire as a conducting channel offers exceptional advantages over conventional memory devices, like small cell size, low-voltage operation, low power consumption, fast programming/erase speed and non-volatility. We successfully fabricated ferroelectric nonvolatile memory devices using both n-type and p-type Si nanowires coated with organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] via a low temperature fabrication process. The devices performance was carefully characterized in terms of their electrical transport, retention time and endurance test. Our p-type Si NW ferroelectric memory devices exhibit excellent memory characteristics with a large modulation in channel conductance between ON and OFF states exceeding $10^5$; long retention time of over $5{\times}10^4$ sec and high endurance of over 105 programming cycles while maintaining ON/OFF ratio higher $10^3$. This result offers a viable way to fabricate a high performance high-density nonvolatile memory device using a low temperature fabrication processing technique, which makes it suitable for flexible electronics.

• 한국정보통신학회논문지
• /
• 제26권5호
• /
• pp.682-687
• /
• 2022

터널링 전계효과 트랜지스터(tunneling field-effect transistor; TFET)로 적층된 3차원 적층형 집적회로(monolithic 3D integrated-circuit; M3DIC)에 대한 연구 결과를 소개한다. TFET는 MOSFET(metal-oxide-semiconductor field-effect transistor)와 달리 소스와 드레인이 비대칭 구조이므로 대칭구조인 MOSFET의 레이아웃과 다르게 설계된다. 비대칭 구조로 인해서 다양한 인버터 구조 및 레이아웃이 가능하고, 그 중에서 최소 금속선 레이어를 가지는 단순한 인버터 구조를 제안한다. 비대칭 구조의 TFET를 순차적으로 적층한 논리 게이트인 NAND 게이트, NOR 게이트 등의 M3DIC의 구조와 레이아웃을 제안된 인버터 구조를 바탕으로 제안한다. 소자와 회로 시뮬레이터를 이용해서 제안된 M3D 논리게이트의 전압전달특성 결과를 조사하고 각 논리 게이트의 동작을 검증한다. M3D 논리 게이트 별 셀 면적은 2차원 평면의 논리게이트에 비해서 약 50% 감소된다.

• 마이크로전자및패키징학회지
• /
• 제12권1호
• /
• pp.59-63
• /
• 2005

금속-강유전체-반도체 전계효과 트랜지스터 (MFS/MFISFET)의 동작 특성을 technology computer-aided design (TCAD)과 simulation program with integrated circuit emphasis (SPICE)를 결합하여 전산모사하는 방법을 제시하였다. 복잡한 강유전체의 동작 특성을 수치해석을 이용하여 해석한 다음, 이를 이용하여 금속-강유전체-반도체 구조에서 반도체 표면에 인가되는 표면 전위를 계산하였다. 계산된 TCAD 변수인 표면 전위를 전계효과 트랜지스터의 SPICE 모델에서 구한 표면 전위와 같다고 보고게이트 전압에 따른 전류전압 특성을 구할 수 있었다. 이와 같은 방법은 향후 MFS/MFISFET를 이용한 메모리소자의 집적회로 설계에 매우 유용하게 적용될 수 있을 것이다.

• Transactions on Electrical and Electronic Materials
• /
• 제12권3호
• /
• pp.93-97
• /
• 2011

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a 0.35 ${\mu}M$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and 1.5 ${\mu}M$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($I_{SUB}$), drain to source leakage current ($I_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

• 한국전기전자재료학회논문지
• /
• 제27권2호
• /
• pp.76-80
• /
• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 추계학술대회 논문집
• /
• pp.21-24
• /
• 2000

Ferroelectric YMnO$_3$ thin films are excellent dielectric materials for high integrated ferroelectric random access memory (FRAM) with metal-ferroelectric-silicon field effect transistor (MFSFET) structure. In this study, YMnO$_3$ thin films were etched with C1$_2$/Ar gas chemistries in inductively coupled plasma (ICP). The maximum etch rate of YMnO$_3$ thin films is 285 $\AA$/min under C1$_2$/Ar of 10/0, 600 W/-200 V and 15 mTorr. The selectivities of YMnO$_3$ over CeO$_2$ and $Y_2$O$_3$ are 2.85, 1.72, respectively. The results of x-ray photoelectron spectroscopy (XPS) reflect that Y is removed dominantly by chemical reaction between Y and Cl, while Mn is removed more effective by Ar ion bombardment than chemical reaction. The results of secondary ion mass spectrometer (SIMS) were equal to these of XPS. The etch profile of the etched YMnO$_3$ film is approximately 65$^{\circ}$and free of residues at the sidewall.