• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.9
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• pp.76-84
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• 1992

The DSP silicon compiler consists of language compiler, module generator, placement tool, router, layout generation tools, and simulator. In this paper, The language compiler, the module generator, placement tool, and simulator were developed and provided for the system designer. The language compiler translates the designer's system description language into the intermediate form file. The intermediate form file expresses the interconnections and specifications of the cells in the cell library. The simulator was developed and provided for the behavioral verification of the DSP system. For its implementation, the event-driven technique and the C$^{++}$ task library was used. The module generator was developed for the layout of the verified DSP system, and generates the functional block to be used in the DSP chip. And then the placement tool determines the appropriate positions of the cells in the DSP chip. In this paper, the placement tool was implemented by Min-Cut and Simulated Annealing algorithm. The placement process can be controlled by the several conditions input by the system designer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1914-1924
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• 2014

In this paper, a small-area cell array method of reducing number of SL drivers requiring large layout areas, where the SL drivers supplying programming currents are routed in the row direction in stead of the column direction for eFuse OTP memory IPs having less number of rows than that of columns such as a cell array of four rows by eight columns, and a core circuit are proposed. By adopting the proposed cell array and core circuit, the layout area of designed 32-bit eFuse OTP memory IP is reduced. Also, a V2V ($=2V{\pm}10%$) regulator necessary for RWL driver and BL pull-up load to prevent non-blown eFuse from being blown from the EM phenomenon by a big current is designed. The layout size of the designed 32-bit OTP memory IP having a cell array of four rows by eight columns is 13.4% smaller with $120.1{\mu}m{\times}127.51{\mu}m$ ($=0.01531mm^2$) than that of the conventional design with $187.065{\mu}m{\times}94.525{\mu}m$ ($=0.01768mm^2$).

• Proceedings of the SAREK Conference
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• 2006.06a
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• pp.885-890
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• 2006

This study presents analysis results for the hybrid system combining solid oxide fuel cell and gas turbine. Two different system layouts(an ambient pressure system and pressurized system) are considered and their design performance are comparatively investigated taking into account critical design factor, the most critical parameter such as turbine inlet temperature, gas turbine pressure ratio, temperature difference at the fuel cell and fuel cell operating temperature are considered as design constraints. Performance variations according to system layout and design parameters are examined in energetic view point.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.4
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• pp.557-564
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• 1986

This paper describes a standard cell placement strategy which consists of three kconsecutive steps` initial placement, iterative placement improvement, and string placement. In the initial placement step, cell placement was done by solving the linear ordering problem for a one-dimensional layout of standard cells and then zigzaging the resultant linear order width in the chip plane. The iterative placement improvement step is based on the iterative pairwise interchange using the estimated total routing length as a figure-or -merit. The string placement is used to reorder cells and terminals in each etandard cell row such that channel routing in the adjacent channels is not blocked by cyclic constraints and needs fewer routing tracks. The placement program is coded in PASCAL and kimplemented on a VAX-11/750 computer. Experimental results for several examples are included.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8B
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• pp.677-686
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• 2012

In the presence of a high power cellular network, picocells are added to a Macro-cell layout aiming to enhance total system throughput from cell-splitting. While because of the different transmission power between macrocell and picocell, and co-channel interference challenges between the existing macrocell and the new low power node-picocell, these problems result in no substantive improvement to total system effective throughput. Some works have investigated on these problems. Pico Cell Range Expansion (CRE) technique tries to employ some methods (such as adding a bias for Pico cell RSRP) to drive to offload some UEs to camp on picocells. In this work, we propose two solution schemes (including cell selection method, channel allocation and serving process) and combine new adaptive frequency partitioning reuse scheme to improve the total system throughput. In the simulation, we evaluate the performances of heterogeneous networks for downlink transmission in terms of channel utilization per cell (pico and macro), call blocking probability, outage probability and effective throughput. The simulation results show that the call blocking probability and outage probability are reduced remarkably and the throughput is increased effectively.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.10
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• pp.595-602
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• 2003

This Paper presents an efficient hybrid techniques for a standard cell placement. The prototype tool adopts a middle-down methodology in which an n${\times}$m grid is imposed over the layout area and cells are assigned to bins forming a global placement. The optimization technique applied in this phase is based on the Relaxation-Based Local Search (RBLS) framework [12］in which a combinatorial search mechanism is driven by an analytical engine. This enables a more global view of the problem and results in complex modifications of the placement in a single search“move.”Details of this approach including a novel placement legalization procedure are presented. When a global placement converges, a detailed placement is formed and further optimized by the optimal interleaving technique[13］. Experimental results on MCNC benchmarking circuits are presented and compared with the Feng Shui's results in［14］. Solution Qualifies are almost the same as the Feng Shui's results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• Journal of the Korea Safety Management & Science
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• v.10 no.2
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• pp.123-132
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• 2008

This study try introduce a cell manufacturing form and to make the productivity in a conveyor line manufacture for the customer requirement and market change. The case research from JIT theory that made the model to make a productivity enhance through the cell line in a conveyor line and U-line. This research was subject with a cosmetics manufacture company, therefor we can raise the quality enhance, personnel expenses and reduction of delivery effectiveness in a stroke types of industry consequently.

• Journal of the Korean Society of Safety
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• v.31 no.4
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• pp.143-149
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• 2016

In this study, a series of numerical simulation of dam break flow was conducted using EFDC model, and input conditions including cell size, time step, and turbulent eddy viscosity were considered to analyze parameter sensitivity. In case of coarse mesh layout, the propagated length of the shock wave front was ${\Delta}_x$ longer than that of other mesh layouts, and the velocity results showed jagged edge, which can be cured by applying fine grid mesh. Turbulent eddy viscosity influenced magnitude of the maximum velocity passing through gate up to 20% and the cell Peclet number less than 2.0 ensured no numerical oscillations.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.59-62
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• 2000

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. From now on, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new algorithm for NPSFs, and neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs are proposed. Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. To consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e., write \longrightarrow refresh \longrightarrow read). Also, we present properties of the algorithm, such as its capability to detect stuck-at faults, transition faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.