• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.451-454
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• 2015

This paper introduces 3 type of OTAs with $0.35-{\mu}m$ standard CMOS technology for Low-Power, Low-Voltage. The first type is a two-stage OTA designed to operate with a 1-V VDD and it has $1.774{\mu}W$ low power consumption. All transistors are operating in strong inversion. It takes Gm-Enhancement techniques to compensate gm, which is lowered by Bulk-Driven technique and has an Wide swing current mirror for low voltage operation and a Class-A output. The second type is a Two-stage OTA designed to operate with a 0.8-V VDD and It has 52nW low power consumption and 112dB high gain. The current mirror uses Composite Transistor binding Gates of two MOSFET to raise Rout which is similar with cascode structure. The third type is a Two-stage OTA designed to operate with a 0.6-V VDD and It has 160nW low power consumption and 72dB high gain. It takes Level Shift technique by Common Gate structure to amplify signals without additional bias voltage at second stage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.1-9
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• 1997

Novel class A CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well standard CMOS process for high-frequency current-mode signal processing were developed. The CCII consists of a regulated current-cell for the voltage input and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated cCII show that the current input impedance is 308 .ohm. and the 3-dB cutoff frequency when used as a voltage amplifier extends beyond 10MHz. The linear dynamic ranges of voltage and current are from -0.5V to 1.5V and from -100.mu.A to +120.mu.A for supply voltage V$\_$DD/ = -V$\_$SS/=2.5V, respectively. The power dissipation is 2 mW and the active chip area is 0.2 * 0.2 [mm$\^$2/].

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.19-26
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• 1997

Novel class AB CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well CMOS process for high-frequency current-mode signal processing were developed. The CCII for low power operation consists of a class AB push-pull stage for the current input, a complementary source follower for the voltage input, and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated CCII show that the current input impedance is 875.ohm. and the bandwidth of flat gain when used as a voltage amplifier extends beyond 4MHz. The power dissipation is 1.25mW and the active chip area is 0.2*0.15[mm$\^$2/].

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3614-3621
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• 2009

In this paper, A CMOS low-voltage current mode integrator is designed. The designed current-mode integrator is based on linear cascode circuit that is newly proposed in this paper. When it is compared with gain(43.7dB) and unity gain frequency(15.2MHz) of the typical current-mirror type current-mode integrator, the proposed linear cascode current-mode integrator achieves high current gain(47.8dB) and unity gain frequency(27.8MHz). And a 5th Chebyshev current-mode filter with 7.03MHz cutoff frequency is designed. The designed all circuits are simulated by HSPICE using 1.8V-$0.18{\mu}m$ CMOS technology.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3638-3644
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• 2009

A CMOS multi-channel low-voltage current mode filter circuit is designed. The designed current-mode filter is based on linear cascode current-mode integrator that is newly proposed in this paper. When it is compared with that of the typical current-mirror type current-mode integrator, the proposed linear cascode current-mode integrator achieves high current gain and unity gain frequency. The designed filter is composed with 5th Chebyshev function and converted to active version by signal flow graph method. We verified that the designed filter can be applied to three-channel basedband, bluetooth, DECT and WCDMA with 0.51MHz~7.03MHz frequency tuning range by Hspice simulation using 1.8V-$0.18{\mu}m$ CMOS technology.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.64-72
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• 1998

In this paper, the design of a current integrator for low-voltage, low-power, and high frequency applications using complementary high swing cascode current-mirror is presented. The proposed integrator decreases output current errors due to non-zero input resistance and non-infinite output resistance of the simple current integrator. As a design example, the 3rd order Butterworth lowpass filter is designed by a leapfrog method. Also, we apply the predistortion design method to reduce the magnitude distortion which occurs at a cutoff frequency by the undesirable phase shift of a lossless current integrator. The designed current-mode filter is simulated and examined by SPICE using 0.8$\mu\textrm{m}$ CMOS n-well process parameters. The simulation results show 20MHz cutoff frequency and 615㎼ power dissipation with a 2V power supply. And the cutoff frequency of the filters can be easily changed by the DC bias current.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.754-764
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• 2001

Class A bipolar second-generation current conveyor (CCII) with low current-input impedance and its offset-compensated CCII for high-accuracy current-mode signal processing are proposed. The CCIIs consist of a regulated current-cell for current input, a emitter follower for voltage input, and a cascode current mirror lot current output. In these architecture, the two input stages are coupled by current mirror to reduce the current input impedance. Experiments show that the CCII has impedance of 8.4 Ω and offset voltage of 40 mV at current input terminal. To reduce this offset, the offset-compensated CCII adopts diode-connected npn and pnp transistor in the proposed CCII. Experiments show that the offset-compensated CCII has current input impedance of 2.1 Ω and offset voltage of 0.05 mV. The 3-dB cutoff frequency of the CCIIs when used as a voltage follower extends beyond 30 MHz. The power dissipation is 7.0 mW

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.34-39
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• 2016

A low-voltage, low-power analog front-end IC for neural recording implant devices is presented. The proposed IC consists of a low-noise neural amplifier and a programmable active bandpass filter to process neural signals residing in the band of 1 Hz to 5 kHz. The neural amplifier is based on a source-degenerated folded-cascode operational transconductance amplifier (OTA) for good noise performance while the following bandpass filter utilizes a low-power current-mirror based OTA with programmable high-pass cutoff frequencies from 1 Hz to 300 Hz and low-pass cutoff frequencies from 300 Hz to 8 kHz. The total recording analog front-end provides 53.1 dB of voltage gain, $4.68{\mu}Vrms$ of integrated input referred noise within 1 Hz to 10 kHz, and noise efficiency factor of 3.67. The IC is designed using $18-{\mu}m$ CMOS process and consumes a total of $3.2{\mu}W$ at 1-V supply voltage. The layout area of the IC is $0.19 mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.201-210
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• 2002

This paper describes a 3.3 (V) low power 4 digit CMOS quaternary to analog converter (QAC) designed with a neuron MOS($\upsilon$MOS) down literal circuit block and cascode current mirror source block. The neuron MOS down literal architecture allows the designed QAC to accept not only 4 level voltage inputs, but also a high speed sampling rate quaternary voltage source LSB. Fast settling time and low power consumption of the QAC are achieved by utilizing the proposed architecture. The simulation results of the designed 4 digit QAC show a sampling rate of 6(MHz) and a power dissipation of 24.5 (mW) with a single power supply of 3.3 (V) for a CMOS 0.35${\mu}{\textrm}{m}$ n-well technology.