• Title/Summary/Keyword: Cascaded Application

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Design and Application of Microstrip Line Photonic Bandgap Structure with a Quarter-Wavelength Transformer for The Modified Characteristics of Stopband (변형된 저지특성을 갖도록 ${\lambda}g$/4 변환기를 정합 시킨 마이크로스트립 라인 포토닉 밴드갭 구조의 설계 및 응용)

  • Kim, Tae-Il;Jang, Mi-Yeong;Park, Ik-Mo;Im, Han-Jo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.37 no.9
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    • pp.38-48
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    • 2000
  • This paper presents the photonic bandgap structure that has a defect mode within a broad stopband. In order to create a broad stopband, we eliminated one of periodic stopbands of PBG structure by using a quarter-wavelength transformer and cascaded another PBG structure having a center frequency corresponding to the eliminated stopband. We have demonstrated that it is a simple and effective method that can solve an overlapping problem of periodic stopband in two cascaded PBG structures.

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Parallel Multi-task Cascade Convolution Neural Network Optimization Algorithm for Real-time Dynamic Face Recognition

  • Jiang, Bin;Ren, Qiang;Dai, Fei;Zhou, Tian;Gui, Guan
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.14 no.10
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    • pp.4117-4135
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    • 2020
  • Due to the angle of view, illumination and scene diversity, real-time dynamic face detection and recognition is no small difficulty in those unrestricted environments. In this study, we used the intrinsic correlation between detection and calibration, using a multi-task cascaded convolutional neural network(MTCNN) to improve the efficiency of face recognition, and the output of each core network is mapped in parallel to a compact Euclidean space, where distance represents the similarity of facial features, so that the target face can be identified as quickly as possible, without waiting for all network iteration calculations to complete the recognition results. And after the angle of the target face and the illumination change, the correlation between the recognition results can be well obtained. In the actual application scenario, we use a multi-camera real-time monitoring system to perform face matching and recognition using successive frames acquired from different angles. The effectiveness of the method was verified by several real-time monitoring experiments, and good results were obtained.

High-Quality Coarse-to-Fine Fruit Detector for Harvesting Robot in Open Environment

  • Zhang, Li;Ren, YanZhao;Tao, Sha;Jia, Jingdun;Gao, Wanlin
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.15 no.2
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    • pp.421-441
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    • 2021
  • Fruit detection in orchards is one of the most crucial tasks for designing the visual system of an automated harvesting robot. It is the first and foremost tool employed for tasks such as sorting, grading, harvesting, disease control, and yield estimation, etc. Efficient visual systems are crucial for designing an automated robot. However, conventional fruit detection methods always a trade-off with accuracy, real-time response, and extensibility. Therefore, an improved method is proposed based on coarse-to-fine multitask cascaded convolutional networks (MTCNN) with three aspects to enable the practical application. First, the architecture of Fruit-MTCNN was improved to increase its power to discriminate between objects and their backgrounds. Then, with a few manual labels and operations, synthetic images and labels were generated to increase the diversity and the number of image samples. Further, through the online hard example mining (OHEM) strategy during training, the detector retrained hard examples. Finally, the improved detector was tested for its performance that proved superior in predicted accuracy and retaining good performances on portability with the low time cost. Based on performance, it was concluded that the detector could be applied practically in the actual orchard environment.

Design and Verification of Improved Cascaded Multilevel Inverter Topology with Asymmetric DC Sources

  • Tarmizi, Tarmizi;Taib, Soib;Desa, M.K. Mat
    • Journal of Power Electronics
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    • v.19 no.5
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    • pp.1074-1086
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    • 2019
  • This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.

Sigma Delta Decimation Filter Design for High Resolution Audio Based on Low Power Techniques (저전력 기법을 사용한 고해상도 오디오용 Sigma Delta Decimation Filter 설계)

  • Au, Huynh Hai;Kim, SoYoung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.11
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    • pp.141-148
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    • 2012
  • A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

An Illumination-Robust Driver Monitoring System Based on Eyelid Movement Measurement (조명에 강인한 눈꺼풀 움직임 측정기반 운전자 감시 시스템)

  • Park, Il-Kwon;Kim, Kwang-Soo;Park, Sangcheol;Byun, Hye-Ran
    • Journal of KIISE:Software and Applications
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    • v.34 no.3
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    • pp.255-265
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    • 2007
  • In this paper, we propose a new illumination-robust drowsy driver monitoring system with single CCD(Charge Coupled Device) camera for intelligent vehicle in the day and night. For this system that is monitoring driver's eyes during a driving, the eye detection and the measure of eyelid movement are the important preprocesses. Therefore, we propose efficient illumination compensation algorithm to improve the performance of eye detection and also eyelid movement measuring method for efficient drowsy detection in various illumination. For real-time application, Cascaded SVM (Cascaded Support Vector Machine) is applied as an efficient eye verification method in this system. Furthermore, in order to estimate the performance of the proposed algorithm, we collect video data about drivers under various illuminations in the day and night. Finally, we acquired average eye detection rate of over 98% about these own data, and PERCLOS(The percentage of eye-closed time during a period) are represented as drowsy detection results of the proposed system for the collected video data.

A four-port stripline circulator using a single ferrite disk (단일 페라이트 공진기를 이용한 4단자 스트립라인 서큘레이터)

  • Kim, Hye-Jin;Nam, Min-Hee;Lee, Jae-Hyun
    • Journal of Satellite, Information and Communications
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    • v.4 no.2
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    • pp.52-56
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    • 2009
  • The design method of a four-port stripline circulator with a single ferrite disk is proposed using Green's function method. The four-port circulator gives the flexibility of the design of the communication system. Two cascaded three-port circulators has been used as a four-port circulator. However, if a four-port circulator with a single ferrite disk replace the present four-port circulator, then it will give less weight and volume and so has the advantage in satellite application.

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A Case Study on Problems of Inverter Application for large Power Plant (대용량 발전소 인버터 적용시의 문제점 사례연구)

  • Ryu, Ho-Seon;Lim, Ick-Hun
    • Proceedings of the KIPE Conference
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    • 2008.06a
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    • pp.568-570
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    • 2008
  • 본 논문은 이차공기송풍기를 가변 회전수 제어하여 소내 소비 전력을 절감하고, 전동기의 직입기동에 의한 스트레스를 줄이기 위하여 실증 적용된 발전소 이차 공기송풍기 구동용 H-브릿지 멀티레벨 인버터에 관한 것이다. H-브릿지 멀티레벨 인버터는 독립적으로 절연된 직류 부를 갖는 저압의 단상 인버터(셀 인버터)를 다수 직렬 접속하여 고압 3상 전압을 출력하는 Cascaded H-브릿지 전압형 인버터이다. 주요내용은 국산 인버터 발전소 현장적용 기술을 바탕으로 대형 인버터 현장 실측 내용과 적용시의 문제점들을 다루어 발전소에 확대 적용에 도움을 주고자한다.

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The Compact UHF CT-Type BandPass Filter with a Mixed Coupling

  • Ju, Jeong-Ho;Kahng, Sung-Tek
    • Journal of electromagnetic engineering and science
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    • v.7 no.3
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    • pp.134-137
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    • 2007
  • This paper presents the design of the compact UHF Bandpass filter of CT-type with a novel mixed coupling topology. In further detail, this new coupling structure mathematically equals the transmission zero that enables particularly the better rejection performance in the stopband without increasing the filter's order. To envision this design concept, we fabricated a microstrip filter whose measurement proves to agree with the predicted performance and the suggested coupling structure reduces the overall size, and will be possibly used in the miniaturized UHF apparatus such as the RFID system.

The Design of Sigma-Delta Modulator for audio signal application (음성신호 처리용 저주파 시그마 델타 변조기 설계)

  • 신경민;장흥석;정대영;정강민
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.152-155
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    • 2000
  • Oversampling modulators based on high-order sigma-delta modulation provide an effective means of achieving high-resolution A/D conversion in a VLSI technology. Because high-order noise shaping great]y reduces the quantization noise in the signal band. This paper introduces a third-order cascaded sigma-delta modulator that is stable for large input level. Modulator was simulated 3.3V single power supply voltage in 0.65$\mu\textrm{m}$ CMOS technology. It achieves 80㏈ SNR for a 20㎑ input signal bandwidth. A lock frequency is 3㎒ that is 80 oversampling ratio.

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