• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.115-122
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• 1997

In this paper, on-chp atomatic tuning circuit, using proposed integration level approximation technique, is designed to tuning of the variation of RC time-constant due to aging or temperature variation, etc. This circuit reduces the error, the difference between code values and real outputs of integrator, which is drawback of presented dual-slope tuning circuit and eliminates modulations of processing signals in integrated circuit due to fixed tuning codes during ordinary operation. This system is made up of simple integrator, A/D converter and digital control circuit and all capacitors are replaced by programed capacitor arrays in this system. This tuning circuit with 4 bit resolution achieves $-9.74{\sim}+9.68%$ of RC time constant error for 50% resistance variation.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.61-64
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• 2000

We fabricated and characterized Low Noise Amplifier (LNA) using MCM-C (Multi-Chip-Module-Cofired) technology for 2.14 GHz IMT-2000 mobile terminal application. First, We designed LNA circuits and simulated it's high frequency characteristics using circuits simulator. For the simulation, we adopted high frequency libraries of all the devices used in LNA samples. By the simulation, Gain was 17 dB and Noise Figure was 1.4 dB. We used multilayer process of LTCC (Low Temperature Co-fired Ceramics) substrate and conductor, resistor pattern for the MCM-C LNA fabrication. We made 2 buried inductors, 2 buried capacitors and 3 buried resistors. The number of the total layers was 6. On the top layer, we patterned microstrip line and pads for the SMT device. We measured the high frequency characteristics, and the results were 14.7 dB Gain and 1.5 dB Noise Figure.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.59-65
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• 2001

Epoxy/$BaTiO_3$composite capacitor films with excellent stability at room temperature, uniform thickness, and electrical properties over a large area ware successfully fabricated. The composite capacitor films with good film formation capability and easy process ability were made from epoxy resin developed for ACF as a matrix and two kinds of $BaTiO_3$powders as fillers to increase the dielectric constant of the composite film. The crystal structure of the powders and its effects on dielectric constant of the films were investigated by X-ray diffraction (XRD). And the optimum amount of dispersant, phosphate ester, was determined by viscosity measurement of suspension. DSC and dielectric property tests were conducted to decide the right curing temperature and the optimum amount of the curing agent. As a result, the capacitors of 7 $\mu \textrm{m}$ thick film with 10 nF/$\textrm{cm}^2$ and low leakage current were successfully demonstrated.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.29 no.6
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• pp.270-275
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• 2019

Mica capacitor is being adopted for high voltage firing unit of guided weapon system because of its superior impact enduring property relative to ceramic capacitor. Reliability of localized mica high voltage capacitors was verified through environmental test like terminal strength test, humidity test, thermal shock test and accelerated life test for application to high voltage firing unit. Failure mode of mica capacitor is a decrease of insulation resistance and its final dielectric breakdown. Main constants of accelerated life model were derived experimentally and voltage constant and activation energy were 5.28 and 0.805 eV respectively. Lifetime of mica capacitor at normal use condition was calculated to be 38.5 years by acceleration factor, 496, and lifetime at accelerated condition and this long lifetime confirmed that mica high voltage capacitor could be applied for firing unit.

• Journal of the Korean Ceramic Society
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• v.42 no.2 s.273
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• pp.94-98
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• 2005

$RuO_2$ is widely studied as a lower electrode material for high dielectric capacitors in DRAM (Dynamic Random Access Memories) and FRAM (Ferroelectric Random Access Memories). In this study, the effects of hydrogen, oxygen, and argon Electron Cyclotron Resonance (ECR) plasma pretreatments on deposited by Metal Organic Chemical Vapor Deposition (MOCVD) $RuO_2$ nucleation was investigated using X-Ray Diffraction (XRD), Scanning Electron Microscopy (SEM), and Atomic Force Microscopy (AFM) analyses. Argon ECR plasma pretreatment was found to offer the highest $RuO_2$ nucleation density among these three pretreatments. The mechanism through which $RuO_2$ nucleation is enhanced by ECR plasma pretreatment may be that the argon or the hydrogen ECR plasma removes nitrogen and oxygen atoms at the TiN film surface so that the underlying TiN film surface is changed to Ti-rich TiN.

• Journal of the Korean Ceramic Society
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• v.42 no.10 s.281
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• pp.649-653
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• 2005

A mono-disperse Ni powders for multilayer ceramic capacitors were prepared in a large scale by solution reduction method using $NiSO_{4}$ $N_{2}$$H_{4}$and NaOH. The exothermic reactions such as Ni-complex formation between highly concentrated $NiSO_{4}$ and $N_{2}$$H_{4}$ and the reduction of $Ni^{2+}$ into Ni provided thermal energy sufficient for spontaneous solution-reduction reaction. Because well-defined Ni particles could be prepared without external heating, the present method was named as 'auto-thermal method'. The formation of Ni­complex, the precipitation of $Ni(OH)_{2}$ gel triggered by NaOH addition, and its reduction into Ni by dissolution-recrystallization route were the reaction mechanism. The preparation of mono-disperse and spherical Ni powder was attributed to uniform distribution of reducing agent $N_{2}$$H_{2}$ within $Ni(OH)_{2}$ gel due to the decomposition of$NiSO_{4}$-$N_{2}$ $H_{4}$ complex.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.15-24
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• 2000

The dielectric relaxation of high-dielectric capacitors could be understood as a dynamic property of the capacitor in the time domain, which is regarded as a primarily important charge loss mechanism during the refresh time of DRAMs. Therefore, the equivalent circuit of the dielectric relaxation of the high-dielectric capacitor is essentially required to investigate its effects on DRAM. Nevertheless, There is not any theoretical method which is generally applied to realize the equivalent circuit of the dielectric relaxation. Recently, we have developed a novel procedure for the circuit modeling of the dielectric relaxation of high-dielectric capacitor utilizing the frequency domain. This procedure is a general method based on theoretical approach. We have also verified the feasibility of this procedure through experimental process. Finally, we successfully investigated the effect of dielectric relaxation on DRAM operation with the obtained equivalent circuit through this new method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.7-16
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• 2000

This paper reports a methodology and its application for extracting cell capacitances and parasitic capacitances in a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitances, we employed finite element method (FEM), The three-dimensional DRAM cell structure is generated by solid modeling based on two-dimensional mask layout and transfer data. To obtain transfer data for generating three-dimensional simulation structure, topography simulation is performed. In this calculation, an exemplary structure comprising 4 cell capacitors with a dimension of $2.25{\times}1.75{\times}3.45{\mu}m^3$, 70,078 nodes with 395,064 tetrahedra were used in ULTRA SPARC 10 workstation. The total CPU time for the simulation was about 25 minutes, while the memory size of 201MB was required. The calculated cell capacitance is 24.34fF per cell, and the influential parasitic capacitances in a stacked DRAM cell are investigated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.52-59
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• 2010

This paper proposes a high-resolution and high-frame rate CMOS image sensor with column-wise cyclic ADC. The proposed ADC uses the sharing techniques of OTAs and capacitors for low-power consumption and small silicon area. The proposed ADC was verified implementing the prototype chip as QVGA image sensor. The measured maximum frame rate is 120 fps, and the power consumption is 130 mW. The power supply is 3.3 V, and the die size is $4.8\;mm\;{\times}\;3.5\;mm$. The prototype chip was fabricated in a 2-poly 3-metal $0.35-{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.14-21
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• 2009

In this paper, a Ka-band 10 W power amplifier module with seven power MMIC bare dies is designed and fabricated using MIC technology which combines multiple MMIC chips on a thin film substrate. Modified Wilkinson power dividers/combiners and CBFGCPW-Microstrip transitions for suppressing resonance and reducing connection loss are utilized for high-gain and high-power millimeter wave modules. A new TTL pulse timing control scheme is proposed to improve output power degradation due to large bypass capacitors in the gate bias circuit. Pulse-mode operation time is extended more than 200 nsec and output power increase of 0.62 W is achieved by applying the proposed scheme to the Ka-band 10 W power amplifier module operating in the pulsed condition of 10 kHz and $5\;{\mu}sec$. The implemented power amplifier module shows a power gain of 59.5 dB and an output power of 11.89 W.