• Journal of Electrical Engineering and Technology
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• 제10권5호
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• pp.2018-2030
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• 2015

A two stage ac drive configuration consisting of a single-phase line commutated rectifier and a three-phase voltage source inverter (VSI) is very common in low and medium power applications. The deterministic pulse width modulation (PWM) methods like sinusoidal PWM (SPWM) could not be considered as an ideal choice for modern drives since they result mechanical vibration and acoustic noise, and limit the application scope. This is due to the incapability of the deterministic PWM strategies in sprawling the harmonic power. The random PWM (RPWM) approaches could solve this issue by creating continuous harmonic profile instead of discrete clusters of dominant harmonics. Insufficient filtering at dc link results in the amplitude distortion of the input dc voltage to the VSI and has the most significant impact on the spectral errors (difference between theoretical and practical spectra). It is obvious that the sprawling effect of RPWM undoubtedly influenced by input fluctuation and the discrete harmonic clusters may reappear. The influence of dc link fluctuation on harmonics and their spreading effect in the VSI remains invalidated. A case study is done with four different filter capacitor values in this paper and results are compared with the constant dc input operation. This paper also proposes an ingenious RPWM, a ripple dosed sinusoidal reference-random carrier PWM (RDSRRCPWM), which has the innate capacity of suppressing the effect of input fluctuation in the output than the other modern PWM methods. MATLAB based simulation study reveals the fundamental component, total harmonic distortion (THD) and harmonic spread factor (HSF) for various modulation indices. The non-ideal dc link is managed well with the developed RDSRRCPWM applied to the VSI and tested in a proto type VSI using the field programmable gate array (FPGA).

• 전기학회논문지
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• 제60권6호
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• pp.1152-1162
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• 2011

In this paper, a single-phase DC-AC inverter using two embedded Z-source converters is proposed. The proposed inverter is composed of two embedded Z-source converters with common DC source and output AC load. The output AC voltage of the inverter is obtained by the difference of output capacitor voltages of each converter. The output voltage of each converter take shape of the asymmetrical AC waveform centering zero voltage. Therefore, the proposed inverter can generate the same output voltage despite low VA rating L-C elements, compared to the conventional inverter using high DC voltage with AC ripple. To verify the validity of the proposed system, the PSIM simulation was achieved under the condition of rapid increase of DC source (110[V]${\rightarrow}$150[V]) and R-load (50[${\Omega}$]${\rightarrow}$300[${\Omega}$]). For controlling the voltage of the inverter system, the one-cycle controller was adopted. As results, the proposed inverter output the constant AC voltage (220[V]rms/60[Hz]) for all conditions. Also, the R-L load and nonlinear diode load were adopted for the proposed inverter loads, and we could know that the its output voltage characteristics were as good as the pure R-load. Finally, the RMS and THD of output AC voltage were examined for the different loads, input DC voltages and reference voltage signals.

• Journal of Power Electronics
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• 제18권4호
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• pp.955-964
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• 2018

In this paper, an active capacitor-diode-switch (CDS) snubber is proposed for L-type current-fed isolated DC-DC converters. The proposed CDS-clamped converter has a number of advantages. It can achieve wide range zero-voltage switching (ZVS) on two switches, a continuous input current with a low ripple, a reduction of one active switch and high efficiency. The operating principles, analysis and parameter design guideline are presented. A 300 W prototype is built to test the proposed converter. Simulation and experimental results are shown at 30 V input voltage and 400 V output voltage.

• Journal of Power Electronics
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• 제16권2호
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• pp.522-531
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• 2016

This paper proposes a new NLC (Nearest Level Control) scheme for MMCs (Modular Multilevel Converters), which offers voltage ripple reductions in the DC capacitor of the SM (Sub-Module), the output voltage harmonics, and the switching losses. The feasibility of the proposed NLC was verified through computer simulations. Based on these simulation results, a hardware prototype of a 10kVA, DC-1000V MMC was manufactured in the lab. Experiments were conducted to verify the feasibility of the proposed NLC in an actual hardware environment. The experimental results were consistent with the results obtained from the computer simulations.

• 전기학회논문지P
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• 제52권4호
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• pp.172-178
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• 2003

This paper examines the application of high voltage static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). This method has the primary advantage that the number of voltage levels can be increased for a given number of semiconductor devices when compared to the conventional control methods. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. From the mathematical model of the system, the design procedures of the circuit parameters L and C are presented in this thesis. To meet the specific total harmonic distortion(THD) and ripple factor of the capacitor voltage, the circuit parameters L and C are designed. Simulated and experimental results are also presented and discussed to validate the proposed schemes.

• Journal of Power Electronics
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• 제12권5호
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• pp.708-714
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• 2012

This paper presents a new interleaved pulse-width modulation (PWM) boost-flyback converter to achieve power factor correction (PFC) and regulate DC bus voltage. The adopted boost-flyback converter has a high voltage conversion ratio to overcome the limit of conventional boost or buck-boost converter with narrow turn-off period. The proposed converter has wide turn-off period compared with a conventional boost converter. Thus, the higher output voltage can be achieved in the proposed converter. The interleaved PWM can further reduce the input and output ripple currents such that the sizes of inductor and capacitor are reduced. Since boundary conduction mode (BCM) is adopted to achieve power factor correction, power switches are turned on at zero current switching (ZCS) and switching losses are reduced. The circuit configuration, principle operation, system analysis, and design consideration of the proposed converter are presented in detail. Finally, experiments conducted on a laboratory prototype rated at 500W were presented to verify the effectiveness of the converter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 전력전자학술대회 논문집
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• pp.421-422
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• 2015

Nowadays, bidirectional DC-DC converters are becoming more into picture for different applications especially electric vehicles. There are many bidirectional DC-DC converters topologies; however, voltage-fed Dual Half-Bridge (DHB) topology has less number of switches as compared to other isolated bidirectional DC-DC converters. Furthermore, voltage fed DHB has galvanic isolation, high power density, reduced size, high efficiency and hence cost effective. Electrolytic capacitors always have problem regarding size and reliability in DC-AC single phase inverters. Therefore, voltage-fed DHB converter is proposed for the purpose of power decoupling to replace electrolytic capacitor by film capacitors. A new control strategy has been developed for 120Hz ripple rejection, and it was verified by simulation.

• 한국산학기술학회논문지
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• 제17권9호
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• pp.21-26
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• 2016

본 논문에서는 휴대 전자기기의 내부 전원단을 위한, CCM/DCM 기능의 이중모드 감압형 DC-DC 벅 컨버터를 제안한다. 제안하는 변환기는 1 MHz의 주파수에서 동작하며, 파워단과 제어블럭으로 이루어진다. 파워단은 Power MOS 트랜지스터, 인덕터, 커패시터, 제어 루프용 피드백 저항으로 구성된다. 제어부는 펄스폭 변조기 (PWM), 오차증폭기, 램프 파 발생기, 오실레이터 등으로 이루진다. 또한 본 논문에서 보상단의 큰 외부 커패시터는, 집적회로의 면적축소를 위하여 CMOS 회로로 구성되는 멀티플라이어 등가 커패시터로 대체하였다. 또한,. 본 논문에서, 보상단의 외부 커패시터는 집적회로의 면적을 줄이기 위하여 곱셈기 기반 CMOS 등가회로로 대체하였다. 또한 제안하는 회로는 칩을 보호하기 위하여 출력 과전압, 입력부족 차단 보호회로 및 과열 차단 보호회로를 내장하였다. 제안하는 회로는 $0.18{\mu}m$ CMOS 공정을 사용하여, 케이던스의 스펙트라 회로설계 프로그램을 이용하여 설계 및 검증을 하였다. SPICE 모의 실험 결과, 설계된 이중모드 DC-DC 벅 변환기는 94.8 %의 피크효율, 3.29 mV의 리플전압, 2.7 ~ 3.3 V의 전압 조건에서 1.8 V의 출력전압을 보였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 전력전자학술대회 논문집
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• pp.189-190
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• 2015

This paper investigates an economic and highly efficient power converter topology and its modulation scheme for 60kW rapid EV charger system. The target system consists of three-phase three-switch buck-type rectifier topology. A new Carrier Based PWM scheme along with its simple implementation using logic gates is introduced in this paper. This PWM scheme replaces the diode rectifier equivalent switching state with an active switching state producing the effectively same current flowing path. As a result, the distortion of input current during the polarity reversal of capacitor line voltage can be mitigated. The proposed modulation technique is confirmed through simulation verification. The proposed modulation technique and its implementation scheme can expand the operation range of the three-phase three-switch buck-type rectifier having ac input and capacitor ripple current of high quality.

• 전기전자학회논문지
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• 제23권1호
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• pp.254-260
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• 2019

본 논문에서는 양방향 dc-to-dc 컨버터의 고장원인, 고장영향, 고장 결과를 파악하기 위한 failure mode and effect analysis(FMEA)와 양방향 컨버터의 위험도를 고려한 fault-tree analysis(FTA)를 통해 고장률을 예측한다. 전기차의 구동전압을 효율적으로 상승시키기 위해 인버터 앞단에 부착되는 양방향 컨버터는 배터리 전력을 dc-link 커패시터로 방전시키는 승압모드와 회생전력을 배터리로 충전시키는 강압모드를 가진다. 양방향 컨버터의 동작 특성을 고려한 FMEA 결과를 바탕으로 컨버터의 위험도를 고려한 고장나무를 설계한다. 전기차 MCU용에 맞는 설계 파라메타를 설정하고 출력전압 리플과 인덕터 전류 리플에 따른 커패시터와 인덕터의 부품 고장률을 분석한다. 또한 동작 온도에 따른 주요부품의 고장률을 MIL-HDBK-217F를 이용하여 구한다. 마지막으로 부품 고장률을 고장나무의 기본 사상의 고장률로 반영하여 컨버터 고장률과 평균고장시간을 예측한다.