• Journal of IKEEE
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• v.23 no.3
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• pp.839-843
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• 2019

This paper demonstrates a variable capacitor using fluids as dielectric material and investigates the possibility of its application to a magnetic resonance microscopy's coil. The capacitor structure was integrated with a microfluidic channel and the capacitance was measured while changing the filling percentage of fluids in the channel. The measured capacitance when filling DI water and mineral oil was changed from 1.7 pF to 12 pF and from 1.7 pF to 2 pF, respectively.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.30 no.3
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• pp.110-116
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• 2020

Grains in the BaTiO₃, which is used for a dielectric layer in MLCC(Multi-Layer Ceramic Capacitor) are necessary to form core/shell structure for a stable TCC(Temperature Coefficient of Capacitance) behavior. The shell property has been deduced from the whole TCC behavior of core/shell structure due to its tiny size, ~ few ㎛. This study demonstrates the individual TCC behavior of the shell phase measured by micro-contact measurement in a temperature range between 35 and 135℃. Pt electrode pairs deposited on an enlarged core/shell structure in a diffusion couple sample made the measurement possible. As a result, the DPT (Diffusion Phase Transition) behavior of the shell phase was revealed as a different TCC behavior from that of the core: a broad peak with T_m at 65℃. This would be also useful experimental data for a modelling that depicts dielectric-temperature behavior of core/shell structure.

• International Journal of Aeronautical and Space Sciences
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• v.17 no.4
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• pp.501-517
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• 2016

Synchronized switch damping (SSD) is a structural vibration control technique in which a piezoelectric patch attached to or embedded into the structure is connected to or disconnected from the shunt circuit in order to dissipate the vibration energy of the host structure. The switching process is performed by a digital signal processor (DSP) which detects the displacement extrema and generates a command to operate the switch in synchronous with the structure motion. Recently, autonomous SSD techniques have emerged in which the work of DSP is taken up by a low pass filter, thus making the whole system autonomous or self-powered. The control performance of the previous autonomous SSD techniques heavily relied on the electrical quality factor of the shunt circuit which limited their damping performance. Thus in order to reduce the influence of the electrical quality factor on the damping performance, a new autonomous SSD technique is proposed in this paper in which a negative capacitor is used along with the inductor in the shunt circuit. Only a negative capacitor could also be used instead of inductor but it caused saturation of negative capacitor in the absence of an inductor due to high current generated during the switching process. The presence of inductor in the shunt circuit of negative capacitor limits the amount of current supplied by the negative capacitance, thus improving the damping performance. In order to judge the control performance of proposed autonomous SSDNCI, a comparison is made between the autonomous SSDI, autonomous SSDNC and autonomous SSDNCI techniques for the control of an aluminum cantilever beam subjected to both single mode and multimode excitation. A value of negative capacitance slightly greater than the piezoelectric patch capacitance gave the optimum damping results. Experiment results confirmed the effectiveness of the proposed autonomous SSDNCI technique as compared to the previous techniques. Some limitations and drawbacks of the proposed technique are also discussed.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.3
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• pp.487-494
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• 2020

In this paper, we propose a current memory circuit design that reduces static power consumption and maximizes the advantages of current mode signal processing. The proposed current memory circuit minimizes the problem in which the current transfer error increases as the data transfer time increases due to clock-feedthrough and charge-injection of the existing current memory circuit. The proposed circuit is designed to insert a support MOS capacitor that maximizes the Miller effect in the current transfer structure capable of low-power operation. As a result, it shows the improved current transfer error according to the memory time. From the experimental results of the chip, manufactured with MagnaChip / SK Hynix 0.35 process, it was verified that the current transfer error, according to the memory time, reduced to 5% or less.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.321-322
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• 2006

The electrical properties of PZT thin film capacitor on TiN/W plug structure were investigated for high density ferroelectric memory devices. In order to enhance the ferroelectric properties of PZT capacitor, the process conditions of bottom electrodes were optimized. The fabricated PZT capacitor on TiN/W plug showed good remanent polarization, leakage current, and contact resistance of TiN/W plug, which were $33\;{\mu}C/cm^2$, $1.2{\times}10^{-6}\;A/cm^2$, and 5.3 ohm/contact, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.6
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• pp.479-486
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• 2021

In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.1
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• pp.38-42
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• 2001

Electric and dielectric(Ba,Sr)$TiO_3$[BST] thin films for emtal-Insulator-Semiconductor(MIS) capacitors have been studied. BST thin films wre deposted on p-Si(100) substrates bythe RF magnetron sputtering with tempratue range of 500~$600^{\circ}C$. The dielectric properties of MIS capacitors consisting of Al/BST/$SiO_2$/Si sandwich structure were evaluated ot redcue the leakage current density. The charge state densities of the MIS capacitors were determined by high frequency (1 MHz) C-V measurement. In order to reduce the leakage current in MIS capacitor, high quality $SiO_2$ layer was deposited on bare p-Si substrate. Depending on the oxygen pressure and substrate temperature both positive and negative polarities of effective oxide charge in the MIS capacitors were evaluated. It is considered that the density of electronic states, generated at the BST/$SiO_2$/p-Si interface due to the asymmetric structure within BST/$SiO_2$/Si structure, and the oxygen vacancy content has influence on the behavior of oxide charge.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.760-763
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• 2003

Low Temperature Cofired Ceramics (LTCC) technology is a promising technology to integrate many devices in a module by embedding passive components. For the module substrate, most LTCC structures have dielectric constants below 10 to reduce signal delay time. Some components, which need high dielectric constants, have not been yet embedded in LTCC module. So, embedding capacitor with high capacitance by applying another dielectrics with high dielectric constants in LTCC is an important issue to maximize circuit density in LTCC module. In this study, electrical properties of embedded capacitor fabricated by dielectric paste of high dielectric constants (K-100) and co-firing behavior with LTCC were investigated. To prevent camber development of co-fired structure, constrained sintering process was tested. Dielectric properties of embedded capacitors were calculated from their capacitance and impedance value. Temperature coefficient of capacitance were also measured.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.1
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• pp.91-102
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• 2013

This paper proposes the improved LCCT(Inductor-Capacitor-Capacitor-Trans) Z-source DC-DC converter (Improved LCCT ZSDC) which can generate the bipolar output voltages according to duty ratio D. The proposed converter has the characteristic and structure of Quasi Z-source DC-DC converter(Quasi ZSDC) and conventional LCCT Z-source DC-DC converter(LCCT ZSDC). To confirm the validity of the proposed method, PSIM simulation and a DSP based experiment were performed for each converter. In case which the input DC voltage is 70V, the bipolar output DC voltage of positive 90V and negative 50V could generate. Also, as comparison result of the capacitor voltage ripple in Z-network and the input current under the same condition for each converter, the voltage stress and the capacitor voltage in Z-network of the proposed method were lower compared with the conventional methods. Finally, the efficiency for each method was investigated according to load variation and duty ratio D.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.59-64
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• 2013

In this paper, a capacitor multiplier with good frequency characteristics has been proposed. Effective capacitance of conventional capacitor multiplier decreases as frequency increases due to internal series resistance. On the other hand, the proposed capacitor multiplier using cascode structure has smaller internal resistance, thus shows good frequency characteristics. Conventional and proposed capacitor multiplier were fabricated using Samsung $0.13{\mu}m$ CMOS process and frequency characteristics of capacitor multipliers were measured using LPF. Measurement results show that the conventional capacitor multiplier has maximum 53% of capacitance error, however the proposed multiplier has less than 10% of capacitance error for the frequency change from 100kHz to 1MHz.