• Journal of Industrial and Engineering Chemistry
• /
• v.68
• /
• pp.129-139
• /
• 2018

The effects of N doping concentration and dopant moieties on the electrochemical properties of nanoporous graphene and their dependence on annealing temperature are investigated. Four types of N moieties - amide, amine, graphitic-N, and oxidized-N - are obtained, which transformed into pyridinic-N and pyrrolic-N upon annealing. The diffusion coefficient (D') of the ions in the electrode is the maximum at $400^{\circ}C$ because of a high level of N doping, whereas the second highest D0 value is obtained at $700^{\circ}C$ owing to a high level of reduction and N doping. The highest specific capacitance is obtained for the sample annealed at $400^{\circ}C$.

• Journal of the Semiconductor & Display Technology
• /
• v.18 no.4
• /
• pp.120-123
• /
• 2019

The effect of surface plasmon on ZTO thin films was investigated. The phenomenon of depletion occurring in the interface of the ZTO thin film created a potential barrier and the dielectric layer of the depletion formed a non-mass particle called plasmon. ZTO thin film represents n-type semiconductor features, and surface current by plasma has been able to obtain the effect of improving electrical efficiency as a result of high current at positive voltage and low current at negative voltage. It can be seen that the reduction of electric charge due to recombination of electronic hole pairs by heat treatment of compound semiconductors induces higher surface current in semiconductor devices.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.12 no.5
• /
• pp.791-796
• /
• 2017

In this study, we investigated the influence of the fabrication process of stacked capacitors on the cell capacitance by using Load Lock (L/L) LPCVD system for dielectric thin film of DRAM capacitor. As a result, it was confirmed that the capacitance difference of about 3-4 fF is obtained by reducing the effective thickness of the oxide film by about $6{\AA}$ compared to the conventional non-L/L device. In addition, Cs was found to be about 3-6 fF lower than the calculated value, even though the measurement range of the thickness of the nitride film as an insulating film was in a normal management range. This is because the node poly FI CD is managed at the upper limit of the spec, resulting in a decrease in cell surface area, which indicates a Cs reduction of about 2fF. Therefore, it is necessary to control the thickness of insulating film and CD management within 10% of the spec center value in order to secure stable Cs.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.13 no.4
• /
• pp.1789-1796
• /
• 2012

In this paper, a new high-efficiency CMOS bridge rectifier for driving RFID tag chips is designed and analyzed. The input stage of the proposed rectifier is designed as a cascade structure connected with two NMOSs for reducing the gate capacitance by circuitry method, which is the main path of the leakage current that is increased when the operating frequency is increased. This gate capacitance reduction technique using the cascade input stage for reducing the gate leakage current is presented theoretically. The output characteristics of the proposed rectifier are derived analytically using its high frequency small-signal equivalent circuit. For the general load resistance of $50K{\Omega}$, the proposed rectifier shows better power conversion efficiencies of 28.9% for 915MHz UHF (for ISO 18000 -6) and 15.3% for 2.45GHz microwave (for ISO 18000-4) than those of 26.3% and 26.8% for 915MHz, and 13.2% and 12.6% for 2.45GHz of compared other two existing rectifiers. Therefore, the proposed rectifier may be used as a general purpose rectifier to drive tag chips for various RFID systems.

• Journal of Electrochemical Science and Technology
• /
• v.6 no.2
• /
• pp.59-64
• /
• 2015

Spherical Li₄Ti₅O₁₂ and Li₄Ti₅O₁₂ carbon nanotube (CNT) composites were synthesized using a colloid system. The electrochemical properties of the composites were thoroughly examined to determine their applicability as hybrid capacitor anodes. The electrical conductivity of the spherical Li₄Ti₅O₁₂-CNT composite was improved over that of the spherical Li₄Ti₅O₁₂ composite. The synthesized composites were utilized as the anode of a hybrid capacitor, which was assembled with an activated carbon (AC) positive electrode. The CNTs attached on the spherical Li₄Ti₅O₁₂ particles contributed to a 51% reduction of the equivalent series of resistance of the Li₄Ti₅O₁₂-CNTs/AC hybrid capacitor compared to the Li₄Ti₅O₁₂/AC hybrid capacitor. Moreover, the Li₄Ti₅O₁₂-CNTs/AC hybrid capacitor showed a larger capacitance than the Li₄Ti₅O₁₂/AC hybrid capacitor; specifically, the Li₄Ti₅O₁₂-CNT/AC hybrid capacitor showed 1.6 times greater capacitance at 40 cycles with a 10 mA cm⁻² loading current density.

• Korean Journal of Materials Research
• /
• v.17 no.2
• /
• pp.96-99
• /
• 2007

The effects of post-annealing of high-k $HfO_2$ thin films grown by atomic layer deposition method were investigated by the annealing treatments of $400-600^{\circ}C$. $Pt/HfO_2/p-Si\;MOS$ capacitor structures were fabricated, and then the capacitance-voltage and current-voltage characteristics were measured to analyze the electrical characteristics of dielectric layers. The X-ray diffraction analyses revealed that the $500^{\circ}C-annealed\;HfO_2$ film remained to be amorphous, and the $600^{\circ}C-annealed\;HfO_2$ film was crystallized. The annealing treatment at $500^{\circ}C$ resulted in the highest capacitance and the lowest leakage current due to the reduction of defects in the $HfO_2$ films and non-crystallization. Our results suggest that post-annealing treatments are a critical factor in improving the characteristics of gate dielectric layer.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.51 no.5
• /
• pp.185-190
• /
• 2002

Capacitor material utilized in the downsizing passive devices and dynamic random access memory(DRAM) requires the physical and electrical properties at given area such as capacitor thickness reduction, relative dielectric constant increase, low leakage current and thermal stability. Common capacitor materials, $SiO_2$, $Si_3N_4$, $SiO_2$/$Si_3N_4$,TaN and et al., used until recently have reached their physical limits in their application to several hundred angstrom scale capacitor. $Ta_2O_{5}$ is known to be a good alternative to the existing materials for the capacitor application because of its high dielectric constant (25 ~35), low leakage current and high breakdown strength. Despite the numerous investigations of $Ta_2O_{5}$ material, there have little been established the clear understanding of the annealing effect on capacitance characteristic and conduction mechanism, design and fabrication for $Ta_2O_{5}$ film capacitor. This study presents the structure-property relationship of reactive-sputtered $Ta_2O_{5}$ MIM capacitor structure processed by annealing in a vacuum. X-ray diffraction patterns skewed the existence of amorphous phase in as-deposited condition and the formation of preferentially oriented-$Ta_2O_{5}$ in 670, $700^{\circ}C$ annealing. On 670, $700^{\circ}C$ annealing under the vacuum, the leakage current decrease and the enhanced temperature-capacitance characteristic stability. and the leakage current behavior is stable irrespective of applied electric field. The results states that keeping $Ta_2O_{5}$ annealed at vacuum gives rise to improvement of electrical characteristics in the capacitor by reducing oxygen-vacancy and the broken bond between Ta and O.

• Journal of IKEEE
• /
• v.7 no.2 s.13
• /
• pp.172-180
• /
• 2003

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/40 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.

• Journal of Sensor Science and Technology
• /
• v.30 no.6
• /
• pp.436-440
• /
• 2021

The impact of the gate length (L_g) on the DC and high-frequency characteristics of indium-rich In_0.8Ga_0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (L_SD) of 0.8 ㎛ with different values of L_g ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (V_T) roll-off behavior against L_g was observed clearly, and the maximum transconductance (g_{m_max}) improved as L_g scaled down to 19 nm. In particular, the device with an L_g of 19 nm with an L_SD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a g_{m_max} of 2.5 mS/㎛, On resistance (R_ON) of 261 Ω·㎛, current-gain cutoff frequency (f_T) of 738 GHz, and maximum oscillation frequency (f_max) of 492 GHz. The results indicate that the reduction of L_g to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.

• Journal of IKEEE
• /
• v.21 no.3
• /
• pp.248-251
• /
• 2017

In this paper, The proposed board is developed by EMI compliant Dash Camera with $360^{\circ}$ omni angle. The proposed board is designed by designing DM and CM input noise reduction circuit and applying active EMI filter coupling circuit. The DM and CM input noise reduction circuit design uses a differential op amp circuit to obtain the DM noise coupled to the input signal via the parasitic capacitance(CP). In order to simplify the circuit by applying the active EMI filter coupling circuit, a noise separator is installed to compensate the noise of the EMI source to compensate the CM and DM active filter simultaneously. In order to evaluate the performance of the board for the proposed EMI response, an authorized accreditation body has confirmed that the electromagnetic certification standard for each frequency band is satisfied.