• Transactions on Electrical and Electronic Materials
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• 제12권1호
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• pp.35-39
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• 2011

An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 $\mu$m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.

• Journal of KIISE:Computer Systems and Theory
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• 제30권5_6호
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• pp.265-272
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• 2003

As VLSI systems become integrated at large-scale, logic fault or delay fault may result from crosstalk noise originated from cross coupling capacitance which exists between two adjacent wires. Because designers in industry do not have means to prevent crosstalk problems, they should check and adjust unsatisfactory designs after all designs are completed, if necessary. In this paper, we analyze how spacing, slew rate, line width, and line length influence the crosstalk, and suggest some solutions for the various factors that nay cause crosstalk problems. we also propose how to optimize the designs by using standardization of noise tables.

• Journal of the Korean Institute of Telematics and Electronics B
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• 제32B권11호
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• pp.1374-1382
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• 1995

In TFT-LCDs, as the display size area becomes larger, and the resolution higher, we have to consider the image degradation effects due to the incorporation of the TFT-LCD parameters such as the data-line resistance, the common electrode resistance, the data-line to common parasitic capacitance, and the output characteristics of driver ICs. One of the degradation effects is crosstalk resulting from the coupling between the source bus-line and common electrode. Since a source signal which represents a large number of display data is supposed to vary frequently, the common signal level is affected through the coupling effect, resulting in the degradation of nearby pixel drive signals. Therefore, we proposed a method to compensate for this source-common electrode coupling effect, we also designed and experimented the feasibility of our crosstalk compensation circuit in the actual TFT-LCD. We saw that the newly designed compensation circuit greatly reduced the crosstalk in display pattern image.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제40권4호
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• pp.74-84
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• 2003

Conventional test algorithms do not effectively detect faults by word-line and bit-line coupling noise resulting from the increase of the density of memories. In this paper, the possibility of faults caused by word-line coupling noise is shown, and new fault model, WLSFs(Word-Line Sensitive Fault) is proposed. We also introduce the algorithm considering both word-line and bit-line coupling noise simultaneously. The algorithm increases probability of faults which means improved fault coverage and more effective test algorithm, compared to conventional ones. The proposed algorithm can also cover conventional basic faults which are stuck-at faults, transition faults and coupling faults within a five-cell physical neighborhood.

• The Transactions of the Korean Institute of Power Electronics
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• 제23권4호
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• pp.247-255
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• 2018

This paper proposes a transformer design of a direct cell-to-cell active cell balancing circuit with a multi-winding transformer for battery management system (BMS) applications. The coupling coefficient of the multi-winding transformer and the output capacitance of MOSFETs significantly affect the balancing current transfer efficiency of the cell balancing operation. During the operation, the multi-winding transformer stores the energy charged in a specific source cell and subsequently transfers this energy to the target cell. However, the leakage inductance of the multi-winding transformer and the output capacitance of the MOSFET induce an abnormal energy transfer to the non-target cells, thereby degrading the transfer efficiency of the balancing current in each cell balancing operation. The impacts of the balancing current transfer efficiency deterioration are analyzed and a transformer design methodology that considers the coupling coefficient is proposed to enhance the transfer efficiency of the balancing current. The efficiency improvements resulting from the selection of an appropriate coupling coefficient are verified by conducting a simulation and experiment with a 1 W prototype cell balancing circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제7권6호
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• pp.1297-1303
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• 2003

This paper propose an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling, ESD of each sensor pixel. The 128${\times}$l44 pixel fingerprint sensor circuit was designed and simulated, and the layout was performed.

• ETRI Journal
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• 제37권1호
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• pp.128-137
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• 2015

In this work, a fishbone-type transmission line employing a comb-type ground plane (FTLCGP) was fabricated on polyethersulfone (PES) substrate, and its RF characteristics were thoroughly investigated. According to the results, it was found that the FTLCGP on PES showed periodic capacitance values much higher than other types of transmission lines due to a coupling capacitance between the signal line and ground, which resulted in a reduction of wavelength and line width. Using the theoretical analysis, we also extracted the bandwidth characteristic of the FTLCGP on PES. According to the result, the FTLCGP structure showed a cut-off frequency of 280 GHz.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.395-398
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• 2004

We developed an a-Si TFT-LCD panel with integrated gate driver circuit using a standard 5-MASK process. To minimize the effect of the a-Si TFT current and LC's capacitance variation with temperature, we developed a new a-Si TFT circuit structure and minimized coupling capacitance by changing vertical architecture above gate driver circuit. Integration of gate driver circuit on glass substrate enables single chip and 3-side free panel structure in a-Si TFT-LCD of QVGA(240$^{\ast}$320) resolution. And using double ASG structure the dead space of TFT-LCD panel could be further decreased.

• Journal of the Korean Institute of Telematics and Electronics
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• 제25권1호
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.

• Proceedings of the Materials Research Society of Korea Conference
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.67.2-67.2
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• 2012

Graphene is expected to have a significant impact in various fields in the foreseeable future. For example, graphene is considered to be a promising candidate to replace indium tin oxide (ITO) as transparent conductive electrodes in optoelectronics applications. We report the tunability of the wavelength of localized surface plasmon resonance by varying the distance between graphene and Au nanoparticles [1]. It is estimated that every nanometer of change in the distance between graphene and the nanoparticles corresponds to a resonance wavelength shift of ~12 nm. The nanoparticle-graphene separation changes the coupling strength of the electromagnetic field of the excited plasmons in the nanoparticles and the antiparallel image dipoles in graphene. We also show a hysteresis in the conductance and capacitance can serve as a platform for graphene memory devices. We report the hysteresis in capacitance-voltage measurements on top gated bilayer graphene which provide a direct experimental evidence of the existence of charge traps as the cause for the hysteresis [2]. By applying a back gate bias to tune the Fermi level, an opposite sequence of switching with the different charge carriers, holes and electrons, is found [3]. The charging and discharging effect is proposed to explain this ambipolar bistable hysteretic switching.