Browse > Article

Crosstalk optimization in high speed VLSI systems  

김기범 (한양대학교 컴퓨터공학과)
신현철 (한양대학교 컴퓨터공학과)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.30, no.5_6, 2003 , pp. 265-272 More about this Journal
Abstract
As VLSI systems become integrated at large-scale, logic fault or delay fault may result from crosstalk noise originated from cross coupling capacitance which exists between two adjacent wires. Because designers in industry do not have means to prevent crosstalk problems, they should check and adjust unsatisfactory designs after all designs are completed, if necessary. In this paper, we analyze how spacing, slew rate, line width, and line length influence the crosstalk, and suggest some solutions for the various factors that nay cause crosstalk problems. we also propose how to optimize the designs by using standardization of noise tables.
Keywords
crosstalk;
Citations & Related Records
연도 인용수 순위
  • Reference
1 M. Kuhlmann, S. S. Sapatnekar. 'Extract and Efficient Crosstalk Estimation', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 20. No. 7. July 2001 pp 858-866   DOI   ScienceOn
2 C.L. Phillips, Signals, systems and Transforms, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 1999, ch. 7
3 J. Cong, D. Z. Pan and P. V. Srinivas. ' Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization', Design Automation Conference, 2001. proceedings of the ASP-DAC 2001. pp 373-378   DOI
4 A. B. Kahng, S. Muddu, and E. Sarto. 'On Switch Factor Based Analysis of Coupled RC Interconnects', Design Automation Conference, 2000. Proceedings 2000 pp 79-84
5 양재석, 김정열, 최준호, 유문현, 공정택, 'Deep Submicron 설계의 interconnect 모델링 자동 비교 분석기(IntView) 개발', 2001 SOC Design conference Volumel pp 775-780
6 T. Gao and C. L. Liu 'Minimum Crosstalk Channel Routing', Computer -Aided Design of Integrated Circuits and Systems, IEEE Transaction on, volume: 15 Issue: 5, May 1996 pp 465-474   DOI   ScienceOn
7 J. Cong and D.Z. Pan, 'Interconnect Estimation and Planning for Deep Submicron Designs', Proc. DAC, pp 507-510   DOI
8 Star-Hspice Manual Volume 4 Applications and Examples v.1999.2 Appendix B. Ideal and Lumped Transmission Lines
9 F. Garcia, P. coll, and D. Auvergne. 'Design of a Slew Rate Controlled Output Buffer', ASIC Conference 1998. proceedings. Eleventh Annual IEEE International, 1998   DOI
10 K. LEUNG 'Controlled Slew rate Output Buffer', IEEE 1988 custom Integrated Circuits Conference