Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Test Algorithm for Word-Line and Bit-line Sensitive Faults in High-Density Memories

고집적 메모리에서 Word-Line과 Bit-Line에 민감한 고장을 위한 테스트 알고리즘

  • 강동철 (디오닉스) ;
  • 양명국 (울산대학교 전기전자정보시스템공학부) ;
  • 조상복 (울산대학교 전기전자정보시스템공학부)
  • Published : 2003.04.01
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Abstract

Conventional test algorithms do not effectively detect faults by word-line and bit-line coupling noise resulting from the increase of the density of memories. In this paper, the possibility of faults caused by word-line coupling noise is shown, and new fault model, WLSFs(Word-Line Sensitive Fault) is proposed. We also introduce the algorithm considering both word-line and bit-line coupling noise simultaneously. The algorithm increases probability of faults which means improved fault coverage and more effective test algorithm, compared to conventional ones. The proposed algorithm can also cover conventional basic faults which are stuck-at faults, transition faults and coupling faults within a five-cell physical neighborhood.

기존의 테스트 알고리즘은 대부분 셀간의 고장에 중심이 맞추어져 있어 메모리의 집적도의 증가와 더불어 일어나는 word-line 과 bit-line 결합 잡음에 의한 고장을 효과적으로 테스트 할 수 없다 본 논문에서는 word-line 결합 capacitance에 의한 고장의 가능성을 제시하고 새로운 고장 모델인 WLSFs(Word-Line Sensitive Faults)을 제안하였다. 또한 word-line 과 bit-line 결합 잡음을 동시에 고려한 알고리즘을 제시하여 고장의 확률을 높였고 고장의 원인을 기존의 고장 모델로는 되지 않음을 보여준다. 제안된 알고리즘은 기존의 기본적인 고장인 고착고장, 천이고장, 그리고 결합고장을 5개의 이웃셀 내에서 모두 검출할 수 있음을 보여준다.

Keywords

References

  1. J.P.Hayes, 'Testing Memories for Single-Cell Pattern-Sensitive Faults,' IEEE Trans. Comput., Vol. C-29, No. 3, March 1980 https://doi.org/10.1109/TC.1980.1675556
  2. J.P.Hayes, 'Detection of Pattern - Sensitive Faults in RAMs,' IEEE Trans. Comput., Vol. C-24, No. 2, pp. 150-157, Feb. 1975 https://doi.org/10.1109/T-C.1975.224182
  3. D.S.Suk and S.M.Reddy, 'Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories,' IEEE Trans. Comput., Vol. C-29, No. 6, pp. 419-429, June 1980 https://doi.org/10.1109/TC.1980.1675601
  4. P.Mazumder and J.K.Patel, 'Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories,' IEEE Trans. Comput., Vol. 38, No. 3, pp. 394-407, March 1989 https://doi.org/10.1109/12.21126
  5. A.J.van de Goor, 'Testing Semiconductor Memories,' John Wiley & Sons LTD., 1991
  6. A.K.Sharma, 'Semiconductor Memories,' IEEE PRESS, pp. 151-154, 1996
  7. S.Chou et al., 'A 60-ns 16Mbit DRAM with a minimized sensing delay caused by bit-line stray capacitance,' IEEE J. Solid State Circuits, Vol. 24, No. 5, pp. 1176-1183, October 1989 https://doi.org/10.1109/JSSC.1989.572575
  8. H.Hidaka et al., 'Twisted Bit-line Architectures for Multi-Megabit DRAM's,' IEEE J. Solid-State Circuits, Vol. 24, No. 1, pp. 21-27, February 1989 https://doi.org/10.1109/4.16297
  9. Y.Watanabe et al., 'Offset Compensating Bit-line Sensing Scheme for High Density DRAM's,' IEEE J. Solid-State Circuits, Vol. 29, No. 1, pp. 9-13, January 1994 https://doi.org/10.1109/4.272089
  10. D.S.Min and D.W. Langer, 'Multiple Twisted Dataline Techiques for Multigiga bit DRAM's,' IEEE J. Solid-State Circuits, Vol. 34, No. 6, pp. 856-864, June 1999 https://doi.org/10.1109/4.766820
  11. J.S.Kim et al., 'A Low-Noise Folded Bit-Line Sensing Architecture for Multigigabit DRAM with Ultrahigh-Density 6F2 cell,' IEEE J. Solid-State Circuits, Vol. 33, No. 7, pp. 1096-1102, July 1998 https://doi.org/10.1109/4.701271
  12. K.Kim and M.Y.Jeong, 'The COB Stack DRAM Cell at Technology Node Below 100nm-Scaling Issues and Directions,' IEEE Trans. Semi., Vol. 15, No. 2, pp. 137-143, May 2002 https://doi.org/10.1109/66.999584
  13. D.C.Kang and S.B.Cho, 'A New Test Algorithm for Bit-Line Sensitive Faults in High-Density Memories,' J. IKEEE, Vol. 5, No. 1, pp. 43-51, January 2001
  14. Dong-Chual Kang, Jong-Hwa Lee, and Sang-Bock Cho, 'A new test algorithm for bit-line sensitive faults in super high-density momories,' KORUS'01 Proceeding, The Fifth Russian-Korean International Symposium on Science and Technology, Volume 1, pp. 198-201, 2001 https://doi.org/10.1109/KORUS.2001.975099
  15. A.Kinoshita et al., 'A study of delay time on bit-lines in megabit SRAMs,' IEICE Trans. Electron Devices, Vol. E75-C, No. 11, November 1992, pp. 1383-1386