• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.9-17
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• 2011

As semiconductor process rapidly developed, the density of chips becomes higher and the space between adjacent lines narrows smaller. This trend increases the capacitance and inductance in interconnects and the coupling-capacitance of adjacent lines grows even bigger than the self-capacitance of themselves, especially in global interconnects. Inductive and capacitive coupling observed in these phenomena may cause serious problems in signal integrity. This paper proposes a codeword generation technique using extra interconnect lines to reduce the crosstalk caused by inductive and capacitive coupling and to reduce dynamic power consumption considering probability of input data. To estimate the performance of the proposed technique, the experimental results have been obtained using FastCap, FastHenry and HSPICE, and it has been shown that the power consumption using the proposed technique has yielded approximately 15% less than the results of the previous technique.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.78-78
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• 2009

In this study, multilayer piezoelectric ceramics was manufactured using the PMW-PNN-PZT ceramics. Then, their physical characteristics for applicaton of electric power generation were investigated according to the numbers of multilayer. With increasing the numbers of multilayer, effective electromechanical coupling factor($k_{eff}$) and capacitance were decreased and increased, respectively.

• The Magazine of the IEIE
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• v.36 no.9
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• pp.61-69
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• 2009

본 기고에서는 반도체 3D IC에서 저전력, 고속 신호 전송을 가능하게 하는 다양한 인터페이스 기술에 대하여 알아보았다. Micro-bump나 TSV와 같이 유선으로 신호를 전송하는 방법과, capacitance나 inductance coupling을 이용하여 무선으로 전송하는 기술을 살펴보았다. 최근 TSV 공정 기술이 많이 발전하여, 앞으로 TSV 인터페이스에 기반한 3D IC가 많이 나올 것으로 기대된다. 무선 인터페이스를 사용할 경우, 특히 inductance coupling을 이용한 경우, 낮은 vdd로도 신호전송이 가능하고, pulse width를 줄일 수 있으며, ESD 보호회로가 필요없어, 저전력으로 신호를 전송할 수 있다.

• The Journal of the Acoustical Society of Korea
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• v.25 no.3E
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• pp.110-114
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• 2006

In a previous theoretical paper, we have derived a unified formula by considering 2-D coupled mode vibrations. The unified formula for electromechanical coupling coefficient of piezoelectric resonator was verified experimentally. The capacitance change near the resonant frequency was investigated to estimate the effective coupling coefficient of the resonator instead of the conventional method based on I-D model. The susceptance spectra were measured for the seven samples of piezoelectric resonator with different aspect ratio. Excellent agreement between theoretical and experimental results was obtained.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.6
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• pp.46-52
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• 1985

A theoretical study of mutual coupling effects between two H-plane coupled microstrip patch antennas is presented. The radiation resistance and slot capacitance of a single micro-strip patch are calculated. To investigate the mutual coupling effects, the even and odd mode characteristic impedance and effective dielectric constants are obtained using the coupled microstrip line model. The S-parameter matrix elements 511,512 are used to study the mutual coupling e(facts in S-band frequency ranges for various patch spacings. Theoretical results and measurements are in good agreement.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.249-252
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• 2003

This paper propose an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog to comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an exective isolation strategy for removing noise and signal coupling of each sensor pixel. The 128$\times$144 pixel fingerprint sensor circuit was designed and simulated, and the layout was performed.

• Journal of Information Display
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• v.5 no.2
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• pp.1-5
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• 2004

We developed an a-Si TFT-LCD panel with integrated gate driver circuit using a standard 5-MASK process. To minimize the effect of the a-Si TFT current and LC's capacitance variation with temperature, we developed a new a-Si TFT circuit structure and minimized coupling capacitance by changing vertical architecture above gate driver circuit. Integration of gate driver circuit on glass substrate enables single chip and 3-side free panel structure in a-Si TFT-LCD of QVGA ($240{\times}320$) resolution. And using double ASG structure the dead space of TFT-LCD panel could be further decreased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.173-176
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• 1999

Continuing improvement of microprocessor performance involves in the devece size. This allow greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However this has led to propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance(RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. Becase of pattering MSSQ (Methylsilsequioxane), we use RIE(Reactive ton Etching) which is a good anisotrgpy. In this study, according as we control a flow rate of CF$_4$/O$_2$ gas, RF power, we analysis by using ${\alpha}$ -step, SEM and AFM,

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4126-4130
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• 2012

In this paper, we proposed planar spiral inductors based on AC coupling for high-frequency wireless signal transmission. Design and characteristics of various structures of the inductor were analyzed. Capacitance between the inductors can be reduced by positioning two thin-film inductors in parallel. So two structures were proposed. First structure is inter-diagonal structure. This structure was made not to overlap the wire part of the paralleled two inductors. Second structure is On-chip type structure that the two thin-film inductors were in parallel but located on diagonal line not to face each other. The resonance in this structure was reduced from twice to once by increasing horizontal distance between the two thin-film inductors, because the capacitance effect between the two thin-film inductors decreases when the distance between the two inductors increases.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.88-97
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• 1994

We describe the design, fabrication, and performance of the optical fiber-photodiode 1$\times$12 arry module using mesa-type InS10.53T GaS10.47TAS/INP 1$\times$12 PIN photodiode array. We fabricated the PIN PD array for high-speed optical fiber parallel data link optimizing quantum efficiency, operating speed sensitivity from the PIN-FET structure, and electrical AC crosstalk. For each element of the array, the diameter of the photodetective area is 80 $\mu$m, the diameter of the p-metal pad is 90 $\mu$m, and the photodiode seperation is 250 $\mu$m to use Si v-groove. Ground conductor line is placed around diodes and p-metal pads are formed in zigzag to reduce Ac capacitance coupling between array elements. The dark current (IS1dT) is I nA and the capacitance(CS1pDT) is 0.9 pF at -5 V. No signifcant variations of IS1dT and CPD from element to element in the array were observed. We calulated the coupling efficiency for 10/125 SMF and 50/125 GI MMF, and measured the responsivity of the PD array at the wavelength is 1.55 $\mu$ m. Responsivities are 0.93 A/W for SMF and 0.96 A/W for MMF. The optical fiber-PD array module is useful in numerous high speed digital and analog photonic system applications.