• 제목/요약/키워드: Capacitance Matrix

검색결과 61건 처리시간 0.025초

새로운 정전용량 계산식물 이용한 대면적 .고화질 TFT-LCD의 화소 특성 시뮬레이션 (Simulations of Pixel Characteristics for Large Size and High Qualify TFT-LCD using a new sophisticated Capacitance Formulas)

  • 윤영준;정순신;김태형;박재우;최종선
    • 한국전기전자재료학회:학술대회논문집
    • /
    • 한국전기전자재료학회 1999년도 춘계학술대회 논문집
    • /
    • pp.613-616
    • /
    • 1999
  • An active-matrix LCD using thin film transistors (TFTs)has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the new set of capacitance models on the pixel operations can be effectively analyzed, The set of models which is adopted from VLSI interconnections calculate more precise capacitance. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

  • PDF

실험적 정전용량 모델과 축적 용량 설계 방법에 따른 TFT-LCD 화소의 동작 특성 (Effects of an Empirical Capacitance Models and Storage Capacitance Types on TFT-LCD Pixel Operations)

  • 윤영준;정순신;박재우;최종선
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 1999년도 하계학술대회 논문집 D
    • /
    • pp.1750-1752
    • /
    • 1999
  • An active-matrix liquid crystal display (LCD) using thin film transistors (TFTs) has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the sate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the new set of capacitance models on the pixel operations can be effectively analyzed. The set of models which is adopted from VLSI interconnections calculate more precise capacitance. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

  • PDF

전자소자로의 응용을 위한 CNT/PVDF 복합막에서 CNT 조성에 의한 정전용량과 출력전류 제어 (Capacitance and Output Current Control by CNT Concentration in the CNT/PVDF Composite Films for Electronic Devices)

  • 이선우;노임준;신백균;김용진
    • 전기학회논문지
    • /
    • 제62권8호
    • /
    • pp.1115-1119
    • /
    • 2013
  • The carbon nanotube/poly-vinylidene fluoride (CNT/PVDF) composite films for the use of electronic devices were fabricated by spray coating method using the CNT/PVDF solution, which was prepared by adding PVDF pellets into the CNT dispersed N-Methyl-2-pyrroli-done (NMP) solution. The CNT/PVDF composite films were peeled off from the glass substrate and were investigated by the scanning electron microscopy, which revealed that the CNTs were uniformly dispersed in the PVDF films and thickness of the films were approximately $20{\mu}m$. The capacitance of the CNT/PVDF films increased dramatically by adding CNTs into the PVDF matrix, and finally saturated approximately 1880 pF. However, the I-V curves didn't show any saturation effect in the CNT concentration range of 0 ~ 0.04 wt%. Therefore we can control the performance of the devices from the CNT/PVDF composite film by adjusting the current level resulted from the CNT concentration with the uniform capacitance value.

분산제가 BaTiO3/에폭시 복합체의 유전특성에 미치는 영향 (Effect of Surfactant Addition on the Dielectric Properties of BaTiO3/epoxy Composites)

  • 이동호;김병국;제해준
    • 한국재료학회지
    • /
    • 제19권11호
    • /
    • pp.576-580
    • /
    • 2009
  • $BaTiO_3$/epoxy composites have been widely investigated as promising materials for embedded capacitors in printed circuit boards. It is generally known that the dielectric constant (K) of the $BaTiO_3$/epoxy composites increases with improvement of the dispersion of $BaTiO_3$ particles in the epoxy matrix that comes from adding surfactant. The influences of surfactant addition on the dielectric properties of the $BaTiO_3$/epoxy composites are reported in the present study. The dielectric constant of the $BaTiO_3$/epoxy composites is not significantly affected by the surfactant addition. However, the temperature coefficient of capacitance increases and the peel strength decreases as the amount of added surfactant increases. The influences of surfactant addition on the dielectric properties of the neat epoxy are also very similar to those of the $BaTiO_3$/epoxy composites. The residual surfactant in the $BaTiO_3$/epoxy composites affects the temperature coefficient of capacitance and the peel strength of the epoxy matrix, which in turn affects the temperature coefficient of capacitance and the peel strength of the $BaTiO_3$/epoxy composites.

고속 집적회로 패키지 인터커넥션을 위한 설계 데이타베이스 (A Design Database for High Speed IC Package Interconnection)

  • 설병수;이창구;박성희;;;유영갑
    • 전자공학회논문지A
    • /
    • 제32A권12호
    • /
    • pp.184-197
    • /
    • 1995
  • In this paper, high speed IC package-to-package interconnections are modeled as lossless multiconductor transmission lines operating in the TEM mode. And, three mathematical algorithms for computing electrical parameters of the lossless multiconductor transmission lines are described. A semi-analytic Green's function method is used in computing per unit length capacitance and inductance matrices, a matrix square root algorithm based on the QR algorithm is used in computing a characteristic impedance matrix, and a matrix algorithm based on the theory of M-matrix is used in computing a diagonally matched load impedance matrix. These algorithms are implemented in a computer program DIME (DIagonally Matched Load Impedance Extractor) which computes electrical parameters of the lossless multiconductor transmission lines. Also, to illustrate the concept of design database for high speed IC package-to-package interconnection, a database for the multi conductor strip transmission lines system is constructed. This database is constructed with a sufficiently small number of nodes using the multi-dimensional cubic spline interpolation algorithm. The maximum interpolation error for diagonally matched load impedance matrix extraction from the database is 1.3 %.

  • PDF

Fabrication of Charge-pump Active-matrix OLED Display Panel with 64 ${\times}$ 64 Pixels

  • Na, Se-Hwan;Shim, Jae-Hoon;Kwak, Mi-Young;Seo, Jong-Wook
    • Journal of Information Display
    • /
    • 제7권1호
    • /
    • pp.35-40
    • /
    • 2006
  • Organic light-emitting diode (OLED) display panel using the charge-pump (CP) pixel addressing scheme was fabricated, and the results show that it is applicable for information display. A CP-OLED panel with 64 ${\times}$ 64 pixels consisting of thin-film capacitors and amorphous silicon Schottky diodes was fabricated using conventional thin-film processes. The pixel drive circuit passes electrical current into the OLED cell during most of the frame period as in the thin-film transistor (TFT)-based active-matrix (AM) OLED displays. In this study, the panel was operated at a voltage level of below 4 V, and this operation voltage can be reduced by eliminating the overlap capacitance between the column bus line and the common electrode.

A Charge-Pump Passive-Matrix Pixel Driver for Organic Light Emitting Diodes

  • Seo, Jong-Wook;Kim, Han-Byul;Kim, Bong-Ok;Kim, Young-Kwan
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 한국정보디스플레이학회 2002년도 International Meeting on Information Display
    • /
    • pp.108-112
    • /
    • 2002
  • A new pixel driving method for organic light-emitting diode (OLED) flat-panel display (FPD) is proposed. The new charge-pump passive-matrix pixel driver consists only of a storage capacitance and a rectifying diode, and no thin-film transistor (TFT) is needed. The new driver not only supplies a constant current to the OLED throughout the whole period of panel scanning like an active-matrix driver, but also provides a highly linear gray-scale control through a pure digital manner.

  • PDF

데이터 배선 용량 최소화를 위한 비정질 실리콘 박막 트렌지스터 배열의 최적화 설계와 구현 (Optimal Design of a-Si TFT Array for Minimization of Data-line Capacitance and Its Implementation)

  • 김창원;윤정기;김선용;김종효
    • 대한의용생체공학회:의공학회지
    • /
    • 제29권5호
    • /
    • pp.392-399
    • /
    • 2008
  • Thin-film transistor (TFT) arrays for an x-ray detector require quite different design concept from that of the conventional active-matrix liquid crystal devices (AM-LCDs). In this paper anew design of TFT array which uses only SiNx for passivation layer is described to meet the detector performance and the product availability simultaneously. For the purpose of optimizing the design parameters of the TFT array, a Spice simulation was performed. As a result, some parameters, such as the TFT width, the data line capacitance, and the storage capacitance, were able to be fixed. The other parameters were decided within a permissible range of the TFT process especially the photolithography process and the wet etch process. Then we adapted the TFT array which had been produced by the proposed design to our prototype model (FDXD-1417 and evaluated it clinically by comparing with a commercial model (EPEX, Hologic, Beford, USA). The results say that our prototype model is slightly better than EPEX system in chest PA images. So we can prove the technical usefulness and the commercial values of the proposed TFT design.

A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure

  • Kim, Si-Nai;Kim, Wan;Lee, Chang-Kyo;Ryu, Seung-Tak
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • 제12권3호
    • /
    • pp.270-277
    • /
    • 2012
  • This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

복합재료 경화모니터링용 유전센서의 해석 (Analysis of the Dielectric Sensor for Cure Monitoring of Composite Materials)

  • 김진수;이대길
    • 대한기계학회논문집
    • /
    • 제19권7호
    • /
    • pp.1563-1572
    • /
    • 1995
  • The on-line cure monitoring during the cure process of fiber reinforced resin matrix composite material is important for the better quality and productivity. Among several cure monitoring methods, the dielectrometry that uses electrodes as its sensor is known to be the most promising method. In this study, the sensitivity of the dielectric sensor for the on-line cure monitoring was analyzed by finite element method and compared to the experimental results. Using the analytical results, the equation for the capacitance of the sensor was derived. Also, the optimal sensor design method was suggested after analyzing several different sensor shapes.