• Title/Summary/Keyword: Capacitance

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Quantification of Rockwool Substrate Water Content using a Capacitive Water Sensor (정전용량 수분센서의 배지 함수량 정량화)

  • Baek, Jeong-Hyeon;Park, Ju-Sung;Lee, Ho-Jin;An, Jin-Hee;Choi, Eun-Young
    • Journal of Bio-Environment Control
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    • v.30 no.1
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    • pp.27-36
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    • 2021
  • A capacitive water sensor was developed to measure the capacitance over a wide part of a substrate using an insulated electrode plate (30 cm × 10 cm) with copper and Teflon attached on either side of the substrate. This study aimed to convert the capacitance output obtained from the condenser-type capacitance sensor into the substrate water content. The quantification experiment was performed by measuring the changes in substrate water weight and capacitance while providing a nutrient solution and by subsequently comparing these values. The substrate water weight and capacitance were measured every 20 to 30 seconds using the sensor and load cell with a software developed specifically for this study. Using a curve-fitting program, the substrate water content was estimated from the output of the capacitance using the water weight and capacitance of the substrate as variables. When the amount of water supplied was increased, the capacitance tended to increase. Coefficient of variation (CV) in capacitance according to the water weight in substrate was greater with the 1.0 kg of water weight, compared with other weights. Thus, the fitting was performed with higher than 1.0 kg, from 1.7 to 6.0 kg of water weight. The correlation coefficient between the capacitance and water weight in substrate was 0.9696. The calibration equation estimated water content from the capacitance, and it was compared with the substrate water weight measured by the load cell.

A CMOS-based Electronically Tunable Capacitance Multipliers

  • Suwannapho, Chonchalerm;Chaikla, Amphawan;Kamsri, Thawatchai;Riewruja, Vanchai
    • 제어로봇시스템학회:학술대회논문집
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    • 2004.08a
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    • pp.1561-1564
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    • 2004
  • A CMOS-based Electronically Tunable Capacitance Multipliers, which can be magnified the value of a grounded unit capacitance, is presented in this article. The multiplication factor is varied by the ratio of the bias currents. The proposed circuit is simple, small in size and suitable for implementing in standard CMOS process. PSPICE simulation results demonstrating the characteristics of the proposed circuit are included.

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Fabrication of capacitance sensor for real time harmful substance mass fraction mesurement (유독물질 질량분율 실시간 측정용 정전용량센서 제작)

  • Kim, Young-Su;Oh, Jeoung Seok
    • 한국연소학회:학술대회논문집
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    • 2014.11a
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    • pp.337-338
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    • 2014
  • In this study, a method of using a capacitance sensor was investigated as a means to measure the mass fraction of a type of harmful substance. Using MEMS process, we developed a capacitance sensor and studied the real time mass fraction with harmful substance mixture liquid.

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An Efficient Three-Dimensional Capacitance Extraction Based on finite Element Method Adopting Variable Division (가변 분할을 적용한 유한 요소법에 의한 3차원 모형의 효율적인 커패시턴스 추출 방법)

  • 김정학;김준희;김석윤
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.52 no.3
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    • pp.116-122
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    • 2003
  • This paper proposes an efficient method for computing the 3-dimensional capacitance of complex structures. The proposed method Is based on Finite Element Method(FEM) and expands the conventional FEM by adopting variable division. This method improves the extraction efficiency 50 times when compared to the conventional FEM with equal division. The proposed method can be used efficiently to extract electrical parameters of on/off-chip interconnects in VLSI systems.

Full HD AMOLED Current-Programmed Driving with Negative Capacitance Circuit Technology

  • Hattori, Reiji;Shim, Chang-Hoon
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.1093-1096
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    • 2008
  • The circuit simulation has been done on the current-programmed AMOLED and shows that the circuit which behaves as a negative capacitance can reduce the effect of parasitic capacitance fixed on the data-line and can accelerate the current programming speed as high as that required in Full HD AMOLED.

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A Study on Calculation of Capacitance Parameter for Interconnection Line in Multilayer Dielectric Media (다층 유전체 매질에서의 Interconnection Line에 대한 Capacitance Parameter 계산에 관한 연구)

  • 김한구;곽계달
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.8
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    • pp.1187-1196
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    • 1989
  • In this paper, a method for computing the capacitance parameter for a multi-interconnection line in a multilayered dielectric region is presented. The number of interconnection lines and the number of dielectric layers are arbitrary, and the interconnection lines are finite cross section or infinite cross section. The surface of lines and dielectric interface are divided into subsection. The surface charge density of each subsection is a constant step-pulse function for each subsection. After the solution of surface charge density is effected by the method of moments, capacitance parameter is calculated.

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A High Density MIM Capacitor in a Standard CMOS Process

  • Iversen, Christian-Rye
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.1 no.3
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    • pp.189-192
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    • 2001
  • A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

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Temperature Variation Capacitance Characteristics of Inverted Staggered TFT (인버티드 스태거형 TFT 캐패시턴스의 온도변화 특성)

  • 정용호;이우선;김남오
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1996.05a
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    • pp.102-104
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    • 1996
  • The fabrication and analytical expression for the temperature dependent capacitance characteristics of inverted staggered hydrogenerated amorphous silicon thin film transistors(a-si :H TFT) from 303k to 363k were presented. The results show that the experimental capacitance-voltage characteristics at several temperatures are easily measured. Capacitance increased exponentially by gate voltage increase and decreased by temperature increase. C/C(max) ratio decreased at higher temperature, C/C(min) ratio increased at higher temperature.

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The Design and Performance Verification of Collocated Capacitance Sensor for Magnetic Bearing (자기베어링과 공위한 축전센서의 설계 및 성능 평가)

  • 유선중;신동원;김종원
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1994.10a
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    • pp.317-322
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    • 1994
  • The design and performance verification of collocated capacitance sensor system for magnetic bearing is presented. Noncollocation between actuators and sensors may cause unstable rotor behavior. The capacitance sensor is not affected by magnetic field. PCB type capacitance sensor is installed between magnetic bearing polse. so, collocation of sensors and actuators can be achieved. Experiment of sensor's static and dynamic charactistics is conducted. Modeling of the rotor system supported by magnetic bearing is made. And performance comparison between simulation and experiment is showed.

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An Optimal Capacitance of RFID Antenna for Auto-Tracking Systems (자동 트래킹 시스템을 위한 RFID 안테나의 최적 Capacitance)

  • Jang, Gee-Young;Rim, Seong-Rak
    • Proceedings of the KAIS Fall Conference
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    • 2011.05a
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    • pp.444-446
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    • 2011
  • RFID(13.56MHz)를 이용한 자동 트래킹 시스템은 기본적으로 RFID 안테나와 리더부, Card(Tag)로 구성된다. 본 논문에서는 RFID 안테나의 크기와 출력 거리에 영향을 미치는 최적 Capacitance 값을 도출하는 방법을 제시한다. 제시한 방법의 타당성을 검토하기 위하여 RFID 안테나의 크기가 $0.0856{\times}0.05398m$이고 출력거리가 10~12cm에 가장 적합한 Capacitance 값을 도출하여 시제품를 설계 제작하여 정상적인 동작 상태를 확인하였다.

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