• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.102-112
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• 2005

In this work, we developed fully integrated broadband MMIC chip set employing CSP(Chip Size Package) for K/Ka band applications. By utilizing an ACF for the RF-CSP, the fabrication process for the packaged amplifier MMIC could be simplified and made cost effective. $STO(SrTi_{3})$ capacitors were employed to integrate the DC biasing components on the MMIC, and LC parallel circuits were employed for DC feed and ESD protection. A pre-matching technique and RC parallel circuit were used to achieve a broadband matching and good stability fer the amplifier MMIC in K/Ka band. The amplifier CSP MMIC exhibited good RF performance over a wide frequency range in K/Ka band. This work is the first report of a fully integrated CSP amplifier MMIC successfully operating in the K/Ka band.

• Journal of Navigation and Port Research
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• v.27 no.2
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• pp.217-221
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• 2003

In this work, we used a novel RF-CSP to develop a broadband amplifier MMIC, including all the matching and biasing components, for Ku and K band applications. By utilizing an ACF for the RF-CSP, the fabrication process for the packaged amplifier MMIC could be simplified and made cost effective. STO (SrTiO$_3$) capacitors were employed to integrate the DC biasing components on the MMIC. A pre-matching technique was used for the gate input and drain output of the FETs to achieve a broadband design for the amplifier MMIC. The amplifier CSP MMIC exhibited good RF performance (Gain of 12.5$\pm$1.5 dB, return loss less than -6 dB, PldB of 18.5$\pm$1.5 dBm) over a wide frequency range. This work is the first report of a fully integrated CSP amplifier MMIC successfully operating in the Ku/K band.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.11 no.3
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• pp.28-32
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• 2002

Recently, the miniature of electric products such as notebook, cellular-phone etc. is apparently appeared, due to the smaller size of the semiconductor chips. As the size of chip gets smaller, the circuit could be easily damaged by the slightest influence, therefore it is important to investigate the machining quality of $\mu$ BGA. This paper deals with machining characteristics of the $\mu$ BGA singulation. The relationships between the singulation face and machining quality of the $\mu$ BGA singulation are investigated. It is confirmed that machining quality improves as the singulation force decreases.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.121-145
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• 2001

Chip Size Packages (CSP) are now widely used in high speed DRAM. The major driving farce of CSP development is its superior electrical performance than that of conventional package. However, the power dissipation of high speed DRAM like DDR or RAMBUS DRAM chip reaches up to near 2W. This fact makes the thermal management methods in DRAM package be more carefully considered. In this study, the thermal performances of 3 type CSPs named $\mu-BGA$^{TM}$$ $UltraCSP^{TM}$ and OmegaCSP$^{TM}$ were measured under the JEDEC specifications and their thermal characteristics were of a simulation model utilizing CFD and FEM code. The results show that there is a good agreement between the simulation and measurement within Max. 10% of $\circledM_{ja}$. And they show the wafer level CSPs have a superior thermal performance than that of $\mu-BGA.$ Especially the analysis results show that the thermal performance of wafer level CSPs are excellent fur modulo level in real operational mode without any heat sink.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.203-207
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• 2002

CSP(Chip Size Packaging) SAW Filter Package에 대해서, 유한요소해석(Finite Element Analysis) 컴퓨터 Simulation 프로그램인 ANSYS를 이용하여 Package의 온도 분포를 해석하였다. 신뢰성(reliability) Test 조건에서 Transient Thermal Simulation을 한 후, 조건을 변화시켜 가면서 Chip 내부 온도가 어떻게 변화하는지 알아보았다. Chip에 1.8 hour 동안 4W의 열원을 주고, 주위는 2$0^{\circ}C$ 자연대류로 놓고 Transient Thermal Simulation한 결과는 약 99$^{\circ}C$로, 허용 가능한 온도인 11$0^{\circ}C$보다 약 11$^{\circ}C$ 낮음을 알 수 있었다. 또한 이는 실험값인 약 95$^{\circ}C$와 유사한 값을 나타내었다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• Journal of the Korean Chemical Society
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• v.54 no.5
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• pp.594-602
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• 2010

Since the requirement of the high density integration and thin package technique of semiconductor have been increasing, the main package type of semiconductor will be a chip scale package (CSP). The changes of diffusion coefficient and moisture content ratio of epoxy resin systems according to the change of liquid type epoxy resin and fillers for CSP applications were investigated. The epoxy resins used in this study are RE-304S, RE310S, and HP-4032D, and Kayahard MCD as hardener and 2-methylimidazole as catalyst were used in these epoxy resin systems. The micro-sized and nano-sized spherical type fused silica as filler were used in order to study the moisture absorption properties of these epoxy molding compound (EMC) according to the change of filler size. The temperature of glass transition (Tg) of these EMC was measured using Dynamic Scanning Calorimeter (DSC), and the moisture absorption properties of these EMC according to the change of time were observed at $85^{\circ}C$ and 85% relative humidity condition using a thermo-hygrostat. The diffusion coefficients in these EMC were calculated in terms of modified Crank equation based on Ficks' law. An increase of diffusion coefficient and maximum moisture absorption ratio with Tg in these systems without filler can be observed, which are attributed to the increase of free volume with Tg. In the EMC with filler, the changes of Tg and maximum moisture absorption ratio with the filler content can be hardly observed, however, the diffusion coefficients of these systems with filler content show the outstanding changes according to the filler size. The diffusion via free volume is dominant in the EMC with micro-sized filler; however, the diffusion with the interaction of absorption according the increase of the filler surface area is dominant in the EMC with nano-sized filler.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.171-174
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• 1997

The great development of semiconductor industry demands the high efficiency and performance of related device, but the pick and place system of semiconductor packaging device can load a few units until nowdays. Although the system can load a lot of units, it can work multiple sort operation. The defect like that causes a low efficiency. Therefore, this paper represents the development of pick and place system which can work multiple sort operation.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.138-141
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• 2002

There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.1-7
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• 2006

A major failure mode for wafer level chip size package (WLCSP) is thermo-mechanical fatigue of solder joints. The mechanical strains and stresses generated by the coefficient of thermal expansion (CTE) mismatch between the die and printed circuit board (PCB) are usually the driving force for fatigue crack initiation and propagation to failure. In a WLCSP process peripheral or central bond pads from the die are redistributed into an area away using an insulating polymer layer and a redistribution metal layer, and the insulating polymer layer affects solder joints reliability by absorption of stresses generated by CTE mismatch. In this study, several insulating polymer materials were applied to WLCSP to investigate the effect of insulating material. It was found that the effect of property of insulating material on WLCSP reliability was altered with a solder ball layout of package.