• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.969_970
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• 2009

본 논문에서는 CPLD를 활용하여 E-bike에 장착 가능한 독립여자권선 영구자석 전동기 구동제어시스템의 설계에 관한 시뮬레이션 및 실험을 수행하였다. E-bike에서 독립여자권선 영구자석 전동기의 적용은 고가의 구동제어시스템으로 인하여 사용에 제한을 가지고 있다. 이러한 문제점의 보완을 위해 고가의 전동기 구동 전용 마이크로컨트롤러의 사용 대신 원칩 마이크로컨트롤러와 CPLD를 활용한 PWM 로직 발생회로를 구현하였으며, 3상 인버터로 구성 된 구동제어시스템을 설계하였다. 또한 최적 설계를 위하여 시뮬레이션 및 실험을 수행하였으며, PI 전류제어를 적용하여 속도-토크 범위가 넓고 여러 우수한 장점을 가진 독립여자권선 영구자석 전동기의 효율 개선을 목표로 하였다.

• Journal of Industrial Technology
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• v.24 no.A
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• pp.91-97
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• 2004

This paper describes the design of a 2-phase stepping motor driver using CPLD(Complex Programmable Logic Device). The driver IC such as L297(SGS-Thomson Microelectronics), which is mostly used has some difficulties in PWM control because of the switching noise of power MOSFETs. It causes current ripple and acoustic noise. To improve theses characteristics, we proposed a new current control method that the output PWM frequency is almost constant using a digital filter. Also we proposed constant current method for 1-2 phase(half step) excitation. The proposed method is implemented with CPLD(Xilinx, XC9572-PC44). Experimental results show the effectiveness of the proposed method.

• Journal of information and communication convergence engineering
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• v.8 no.5
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• pp.534-538
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• 2010

Efficient control of a marine engine requires an engine control unit (ECU) system that handles fast and precise signal processes for in-coming and out-going signals from fast running engines. In order to handle these roles, the sequential control has been adapted in the ECU system in small and medium size ship engines, which has caused high production cost and complexity of the system. Hence, this paper is focused on developing an distributed ECU system for high speed and high precision control of a marine engine by efficiently combining a CPLD chip and a microprocessor. By sharing load at the MCU with the designed CPLD chip, we could achieve in driving a marine engine with high speed and precise control so that the ECU board has been simplified and its production cost has been reduced.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.361-364
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• 2002

In this paper, we consider the problem of CLB based CPLD technology mapping for power minimization in combinational circuit. The problem has been previously proved to be NP-hard, and hence we present an efficient heuristic algorithm for it. The main idea of our algorithm is to exploit the "cut enumeration" and "feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. However, for the consideration of both run time and memory space, only a fixed-number of solutions are selected and stored by our algorithm. To facilitate the selection process, a method that correctly calculates the estimated power consumption for each mapped sub-circuit is developed. The experimental results show that our approach is shown a decrease of 30.5% compared with DDMAP and that of 15.63% for TEMPLA in the Power consumption.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.683-686
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• 2002

본 논문은 시간 제약 조건하에서 수행 시간을 개선한 CPLD 기술 매핑 알고리즘을 제안하였다. 제안된 기술 매핑 알고리즘은 주어진 시간 제약 조건을 고려하여 가장 빠른 시간에 기술 매핑을 수행 할 수 있도록 속도의 개선에 중점을 두었다. 입력된 회로를 DAG로 표현한 후 입력부터 출력의 방향으로 노드들을 검색하여 매핑 가능 클러스터를 생성한다. 생성된 매핑 가능 클러스터들 중에서 시간 제약 조건에 적합한 매핑 가능 클러스터를 선택하여 기술 매핑을 수행함으로서 전체 수행 시간이 다른 알고리즘에 비해 빠르게 수행된는 결과를 나타내었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.602-605
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• 2000

Recently, a study of intellectual smell recognition system is applied for the various fields such as control of food processing and survey of decay. A basic gas recognition system was implemented gases using four metal oxides semiconductor sensors as inputs. A CPLD chip of twenty thousand gates level was used for this purpose. The CPLD chip was designed and the availability of the one chip smell recognition system was tested.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.686-692
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• 2002

본 논문은 Pyroelectric Sensor의 신호를 입력으로 받아 Stepping Motor 제어신호를 출력하는 Controller를 VHDL을 이용하여 ALTERA사의 EPM7128SLC84-7 CPLD칩으로 구현하여 자동문을 제작하였다. 동작은 센서부에서 사람을 감지하여 출력한 신호를 CPLD에서 받아들여 Stepping Motor구동부 회로의 제어신호로 사용하여 문을 동작시켰다.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.2
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• pp.61-69
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• 2003

In this paper, we developed the U parameter test system which inspects the property of DC parameter for semiconductor products. The developed system is interfaced by IBM-PC. It is consisted of CPLD part, ADC (Analogue to Digital Converter), DAC (Digital to Analogue Converter), voltage/current source, variable resistor and measurement part. In the proposed system, we have designed the constant voltage source and the constant current source in a part. The CPLD part is designed by VHBL, which it generates the control and converts the serial data to parallel data. The proposed system has two test channels and it operates VFCS mode and CFVS mode. The range of test voltage is from 0[V] to 100[V], and the range of test current is from 0[mA] to 100[mA)]. The diode is tested. The test results have a good performance.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.9-17
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• 1999

In this paper, we propose a new technology mapping algorithm for CPLD under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces delay time and the number of CLBs much more than the existing tools of technology mapping algoritm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.12
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• pp.1248-1255
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• 2003

High-speed QPSK demodulator has been one important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes Zero-Crossing IF-level(ZCIF) QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. ZCIF QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tracking to fabricate FPGA chip. The testing results of the implemented onto CPLD-FLEX10K chip show demodulation speed is reached up to 2.6［Mbps］. Actually in case of designing by ASIC, its speed may be faster than CPLD by 5 times. Therefore, it is possible to fabricate the ZCIF QPSK demodulator with speed of 10 Mbps.