• Journal of IKEEE
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• v.18 no.2
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• pp.228-233
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• 2014

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

• Journal of the Korean Society of Industry Convergence
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• v.5 no.1
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• pp.39-43
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• 2002

In present much CMOS devices used in VLSI circuit and Logic circuit. With increasing a number of device in VLSI, the confidence becomes more serious. This paper describe the mechanism of breakdown on CMOS, especially n-MOS, based on Hydro Dynamic model with device self-heating. Additionally, illustrate the CMOS latch-up characteristics on simplified device structure on this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.83-91
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• 2000

This paper presents a new technique to reduce a large interconnect circuit with tens of thousands of elements into the one that is small enough to be analyzed by circuit simulators such as SPICE. This technique takes a fundamentally different approach form the conventional methods based on the interconnect circuit structure analysis and several rules based on the Elmore time constant. The time moments are computed form the circuit consisting of the interconnect circuit and the CMOS gate driver model computed by the AWE technique. Then, the equivalent RC circuit is synthesized from those moments. The characteristics of the driving CMOS gate can be reflected with the high degree of accuracy and the size of the compressed circuit is determined by the number of output nodes regardless of the size of the original interconnect circuits. This technique has been implemented in C language, applied to several interconnect circuits driven by a 0.5${\mu}m$ CMOS gate and the equivalent RC circuits with more than 99% reduction ratio and accuracy with 1 ~ 10% error in therms of propagation delays were obtained.

• ETRI Journal
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• v.30 no.5
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.3
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• pp.134-142
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• 2005

The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.

• Transactions on Electrical and Electronic Materials
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• v.4 no.3
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• pp.5-9
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• 2003

In this paper, a layout-based CMOS RF model for RFIC's including the capacitance effect, the skin effect, and the proximity effect between metal lines on the Si surface is proposed for the first time for accurately predicting the RF behavior of CMOS devices. With these RF effects, the RF equivalent circuit model based on the layout of the multi-finger gate transistor is presented. The capacitances between metal lines on the Si surface are modeled with the layout. And the skin effect is modeled to the equivalent ladder circuit of metal line. The proximity effect is modeled by adding the mutual inductance between cross-coupled inductances in the ladder circuit representation. Compared to the BSIM 3v3 and other models, the proposed RF model shows better agreements with the measured data and shows well the frequency dependent behavior of devices in GHz ranges.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.270-274
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• 2008

This paper proposes an advanced signal processing circuit for a fingerprint sensor based on ridge resistivity. A novel fingerprint integrated sensor using ridge resistivity variation resulting from ridges and valleys on the fingertip is presented. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. The sensor circuit blocks were designed and simulated in a standard CMOS 0.35 ${\mu}m$ process.

• Journal of Electrical Engineering and Technology
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• v.8 no.5
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• pp.1182-1187
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• 2013

Transient radiation is emitted during a nuclear explosion and causes fatal errors as upset and latch-up in CMOS circuits. This paper proposes the transient radiation SPICE models of NMOS, PMOS, and INVERTER based on the transient radiation analysis using TCAD (Technology Computer Aided Design). To make the SPICE model of a CMOS circuit, the photocurrent in the PN junction of NMOS and PMOS was replaced as current source, and a latch-up phenomenon in the inverter was applied using a parasitic thyristor. As an example, the proposed transient radiation SPICE model was applied to a CMOS NAND circuit. The CMOS NAND circuit was simulated by SPICE and TCAD using the 0.18um CMOS process model parameter. The simulated results show that the SPICE results were similar to the TCAD simulation and the test results of commercial CMOS NAND IC. The simulation time was reduced by 120 times compared to the TCAD simulation.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1561-1564
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• 2004

A CMOS-based Electronically Tunable Capacitance Multipliers, which can be magnified the value of a grounded unit capacitance, is presented in this article. The multiplication factor is varied by the ratio of the bias currents. The proposed circuit is simple, small in size and suitable for implementing in standard CMOS process. PSPICE simulation results demonstrating the characteristics of the proposed circuit are included.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.73-77
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• 2003

This paper presents a high-speed algorithmic analog-to-digital converter (ADC), which is based on gray coding. The realization method makes use of a two-input maximum circuit to provide a high-speed operation and a low-distortion in the transfer characteristic. The proposed ADC based on the CMOS integrated circuit technique is simple and suitable for implementing a highresolution ADC. The performances of the proposed circuit were studied using the PSPICE analog simulation program. The simulation-results verifying the circuit performances are agreed with the expected values.