• 전기전자학회논문지
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• 제18권2호
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• pp.228-233
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• 2014

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

• 한국산업융합학회 논문집
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• 제5권1호
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• pp.39-43
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• 2002

In present much CMOS devices used in VLSI circuit and Logic circuit. With increasing a number of device in VLSI, the confidence becomes more serious. This paper describe the mechanism of breakdown on CMOS, especially n-MOS, based on Hydro Dynamic model with device self-heating. Additionally, illustrate the CMOS latch-up characteristics on simplified device structure on this paper.

• 대한전자공학회논문지SD
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• 제37권1호
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• pp.83-91
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• 2000

본 논문은 수 만 개 이상의 소자로 구성된 대규모 배선 회로를 SPICE와 같은 회로 시뮬레이터로 분석할 수 있도록 그 규모를 축소 시키는 새로운 방법을 제안하고 있다. 이 방법은 배선 회로의 구조 분석과 Elmore 시정수에 바탕을 둔 여러 가지 규칙들을 사용하여 회로 소자 개수를 줄여나가는 기존의 방법과 근본적으로 다른 접근 방식이다. AWE 기법을 사용하여 CMOS 게이트 구동 측성 모델을 구하고, 이 모델에 배선 회로를 연결하여 타임 모멘트를 계산한 다음, 이와 동일한 모멘트를 갖는 등가 RC 회로를 합성하는 과정을 거친다. 이 방법을 사용하면 배선 회로를 구동하는 CMOS 게이트의 특성을 높이는 수준의 정확도로 방영할 수 있을 뿐만 아니라, 압축된 회로의 크기가 원래 배선 회로에 포함되어 있던 소자의 개수와 관계없이 출력 노드의 개수에 비례하여 결정되므로, 대규모 배선 회로에 대해서 압축율이 극히 우수하다. 이 방법을 C 프로그램으로 구현하여 0.5${\mu}m$ CMOS ASIC 제품에 적용한 결과, 99% 이상의 극히 우수한 압축율을 보였으며, 원래의 배선 회로 대비 지연 시간 측면에서 1~10%의 오차를 갖는 정확도를 나타내었다.

• ETRI Journal
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• 제30권5호
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

• 융합신호처리학회논문지
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• 제6권3호
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• pp.134-142
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• 2005

전류모드 CMOS 회로기반 다치 논리 회로가 최근에 구현되고 있다. 본 논문에서는 4-치 Unary 다치 논리 함수를 전류모드 CMOS 논리 회로를 사용하여 합성하였다. 전류모드 CMOS(CMCL)회로의 덧셈은 각 전류 값들이 회로비용 없이 수행될 수 있고 또한 부의 논리 값은 전류흐름을 반대로 함으로써 쉽게 구현이 가능 하다. 이러한 CMCL 회로 설계과정은 논리적으로 조합된 기본 소자들을 사용하였다. 제안된 알고리듬을 적용한 결과 트랜지스터의 숫자를 고려하는 기존의 기법보다 더욱 적은 비용으로 구현할 수 있었다. 또한 비용-테이블 기법의 대안으로써 Unary 함수에 대해서 범용 UUPC(Universal Unary Programmable Circuit) 소자를 제안하였다.

• Transactions on Electrical and Electronic Materials
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• 제4권3호
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• pp.5-9
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• 2003

In this paper, a layout-based CMOS RF model for RFIC's including the capacitance effect, the skin effect, and the proximity effect between metal lines on the Si surface is proposed for the first time for accurately predicting the RF behavior of CMOS devices. With these RF effects, the RF equivalent circuit model based on the layout of the multi-finger gate transistor is presented. The capacitances between metal lines on the Si surface are modeled with the layout. And the skin effect is modeled to the equivalent ladder circuit of metal line. The proximity effect is modeled by adding the mutual inductance between cross-coupled inductances in the ladder circuit representation. Compared to the BSIM 3v3 and other models, the proposed RF model shows better agreements with the measured data and shows well the frequency dependent behavior of devices in GHz ranges.

• Journal of information and communication convergence engineering
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• 제6권3호
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• pp.270-274
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• 2008

This paper proposes an advanced signal processing circuit for a fingerprint sensor based on ridge resistivity. A novel fingerprint integrated sensor using ridge resistivity variation resulting from ridges and valleys on the fingertip is presented. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. The sensor circuit blocks were designed and simulated in a standard CMOS 0.35 ${\mu}m$ process.

• Journal of Electrical Engineering and Technology
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• 제8권5호
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• pp.1182-1187
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• 2013

Transient radiation is emitted during a nuclear explosion and causes fatal errors as upset and latch-up in CMOS circuits. This paper proposes the transient radiation SPICE models of NMOS, PMOS, and INVERTER based on the transient radiation analysis using TCAD (Technology Computer Aided Design). To make the SPICE model of a CMOS circuit, the photocurrent in the PN junction of NMOS and PMOS was replaced as current source, and a latch-up phenomenon in the inverter was applied using a parasitic thyristor. As an example, the proposed transient radiation SPICE model was applied to a CMOS NAND circuit. The CMOS NAND circuit was simulated by SPICE and TCAD using the 0.18um CMOS process model parameter. The simulated results show that the SPICE results were similar to the TCAD simulation and the test results of commercial CMOS NAND IC. The simulation time was reduced by 120 times compared to the TCAD simulation.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1561-1564
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• 2004

A CMOS-based Electronically Tunable Capacitance Multipliers, which can be magnified the value of a grounded unit capacitance, is presented in this article. The multiplication factor is varied by the ratio of the bias currents. The proposed circuit is simple, small in size and suitable for implementing in standard CMOS process. PSPICE simulation results demonstrating the characteristics of the proposed circuit are included.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.73-77
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• 2003

This paper presents a high-speed algorithmic analog-to-digital converter (ADC), which is based on gray coding. The realization method makes use of a two-input maximum circuit to provide a high-speed operation and a low-distortion in the transfer characteristic. The proposed ADC based on the CMOS integrated circuit technique is simple and suitable for implementing a highresolution ADC. The performances of the proposed circuit were studied using the PSPICE analog simulation program. The simulation-results verifying the circuit performances are agreed with the expected values.