• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.361-364
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• 1999

A 200 MHz CMOS transconductor using translinear cells is presented. It adopts a cascade circuit consisting of a voltage follower(VF), a resistor, and a current follower(CF). The translinear cell which has substancely high-frequency is used as the VF and CF, respectively Simulation results show that the proposed transconductors have the 3-㏈ frequency of a 200 MHz, and the dynamic range of $\pm$2.5 V for a supply voltage $\pm$3 V.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.82-85
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• 2002

A compact rail to rail CMOS voltage follower is presented. The circuit is based on the symmetrical class AB voltage follower and can operate under supply voltages of ${\pm}$ 1.5 V. The proposed circuit has power dissipation of 5.2㎽ under quiescent condition and can drive ${\pm}$1.25 V to 250$\Omega$ load with a total harmonic distortion of less than 0.5 percent and cut off frequency of 237 ㎒. Although simple, the proposed circuit enables the output transistors to drive load efficiently.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1561-1564
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• 2004

A CMOS-based Electronically Tunable Capacitance Multipliers, which can be magnified the value of a grounded unit capacitance, is presented in this article. The multiplication factor is varied by the ratio of the bias currents. The proposed circuit is simple, small in size and suitable for implementing in standard CMOS process. PSPICE simulation results demonstrating the characteristics of the proposed circuit are included.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.61-64
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• 2000

This paper describes a RF Down-Conversion Mixer for mobile communication systems. This circuit achieves low voltage operation and low power consumption by reducing stacked devices of conventional gilbert cell mixer. In order to reduce stacked devices, we use source-follower structure. The proposed RF Down-Conversion mixer operates up to 1.85GHz at 1.5V power supply with 0.25um CMOS technology and consumes 2.2mA.

• 센서학회지
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• 제26권4호
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• pp.223-227
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• 2017

Conventional CMOS image sensors (CISs) have a trade-off relationship between dynamic range and sensitivity. In addition, their sensitivity is determined by the photodiode capacitance. In this paper, CISs that consist of dual-sensitivity photodiodes in a unit pixel are proposed for achieving wide dynamic ranges. In the proposed CIS, signal charges are generated in the dual photodiodes during integration, and these generated signal charges are accumulated in the floating-diffusion node. The signal charges generated in the high-sensitivity photodiodes are transferred to the input of the comparator through an additional source follower, and the signal voltages converted by the source follower are compared with a reference voltage in the comparator. The output voltage of the comparator determines which photodiode is selected. Therefore, the proposed CIS composed of dual-sensitivity photodiodes extends the dynamic range according to the intensity of light. A $94{\times}150$ pixel array image sensor was designed using a conventional $0.18{\mu}m$ CMOS process and its performance was simulated.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.951-954
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• 2003

A CMOS second generation current conveyor, which can be operated from a low-voltage power supply, is presented in this article. The proposed circuit is simple, small in size and suitable for implementing in standard CMOS process. It provides the resistance at port X lower than 3.5${\Omega}$. The bandwidth of the transfer characteristic extends beyond 326MHz. PSPICE simulation results demonstrating the characteristics of the proposed circuit are included.

• 전자공학회논문지C
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• 제34C권10호
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• pp.19-26
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• 1997

Novel class AB CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well CMOS process for high-frequency current-mode signal processing were developed. The CCII for low power operation consists of a class AB push-pull stage for the current input, a complementary source follower for the voltage input, and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated CCII show that the current input impedance is 875.ohm. and the bandwidth of flat gain when used as a voltage amplifier extends beyond 4MHz. The power dissipation is 1.25mW and the active chip area is 0.2*0.15[mm$\^$2/].

• 센서학회지
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• 제19권1호
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• pp.25-30
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• 2010

This paper presents a low noise CMOS regulator for a low power capacitive sensor interface in a $0.5{\mu}m$ CMOS standard technology. Proposed LDO regulator circuit consist of a voltage reference block, an error amplifier and a new buffer between error amplifier and pass transistor for a good output stability. Conventional source follower buffer structure is simple, but has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide band OTA instead of source follower structure for a buffer. From SPICE simulation results, we got 0.8 % line regulation and 0.18 % load regulation.

• ETRI Journal
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• 제39권3호
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• pp.373-382
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• 2017

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of $433.80{\mu}V/mA$ and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of $1{\mu}s$. The total current consumption is $17.88{\mu}V/mA$ (for a 0.9 V supply voltage).

• 한국산학기술학회논문지
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• 제11권4호
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• pp.1222-1228
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• 2010

고속 PMIC를 위한 빠른 천이 응답 시간을 가지는 CMOS LDO 레귤레이터를 설계하였다. 제안하는 LDO 레귤레이터 회로는 기준전압회로와 오류증폭회로, 파워 트랜지스터 등으로 이루어지며, 출력전압의 안정성을 높이기 위하여 오류증폭 회로와 파워 트랜지스터 사이에 버퍼로써 2단 광대역 OTA를 추가하였다. 기존의 연구에서 제안된 가장 간단하게 구현할 수 있는 버퍼로는 소스팔로워 구조가 있으나, 출력 스윙이 좁고 신호 대 잡음비가 저하되는 문제점이 있었다. 본 논문에서는 2단 광대역 OTA를 버퍼로 사용하여 LDO 전압 레귤레이터의 출력 특성을 개선하였다. $0.5{\mu}m$ CMOS 공정을 이용하여 모의실험 한 결과, 라인 레귤레이션은 16 mV/V, 부하 레귤레이션 0.007 %/mA를 얻었다.