• Journal of the Semiconductor & Display Technology
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• v.3 no.4
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• pp.29-32
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• 2004

Fully depleted Silicon-on-Insulator (FD-SOI) devices lead to better electrical characteristics than bulk CMOS devices. However, the presence of a thin top silicon layer and a buried SiO2 layer causes self-heating due to the low thermal conductivity of the buried oxide. The electrical characteristics of FDSOI devices strongly depend on the path of heat dissipation. In this paper, we present a new three-dimensional (3-D) analysis technique for the self-heating effect of the finger-type and bar-type transistors. The 3-D analysis results show that the drain current of the finger-type transistor is 14.7% smaller than that of the bar-type transistor due to the 3-D self-heating effect. We have learned that the rate of current degradation increases significantly when the width of a transistor is smaller that a critical value in a finger-type layout. The current degradation fro the 3-D structures of the finger-type and bar-type transistors is investigated and the design issues are also discussed.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.6
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• pp.231-237
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• 2016

This paper presents a multiband low phase noise CMOS VCO with wide frequency tunability using switched bondwire inductor bank. The combination of bondwire inductor and CMOS switch transistor enhances frequency tunability and improves phase noise characteristics. The proposed multiband VCO operates from 2.3GHz to 6.3GHz with phase noise of -136dBc/Hz and -122dBc/Hz at 1 MHz offset frequency, respectively. Switched bondwire inductor bank shows high quality factor(Q) at each frequency band, which allows better tradeoff between phase noise and power consumption. The proposed VCO is designed in TSMC 0.18um CMOS process and consumes 7.2 mW power resulting in figure of merit(FOM) of -189.3dBc/Hz at 1 MHz offset from 6GHz carrier frequency.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.52-58
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• 2001

This paper describes a TTL-to-CMOS input buffer of an SRAM which dissipates a small operating power dissipation. The input buffer utilizes a transistor structure with latch circuit controlled by a internal activation clock pulse. During the low state of that pulse, input buffer is disabled to eliminate dc current. Otherwise, the input buffer operates normally. Simulation results showed that the power-delay product of the purposed input buffer is reduced by 33.7% per one input.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.877-882
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• 2016

In this paper, a novel CMOS high Q factor 2-port active inductor has been proposed. The proposed circuit is designed by cascading basic gyrator-C structural active inductors and attaching the feedback LC resonance circuit. This LC resonator can compensate parasitic capacitance of transistor and can improve Q factor over wide frequency range. The proposed circuit was fabricated and simulated using 65 nm Samsung RF CMOS process. The fabricated circuit shows inductance of above 2 nH and Q factor higher than 40 in the frequency range of 1~6 GHz.

• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.236-242
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• 2021

In this paper, we report the fabrication of the tip-on-gate of a field-effect-transistor (ToGoFET) probe using a standard complementary metal-oxide-semiconductor (CMOS) process and the performance evaluation of the fabricated probe. After the CMOS process, I-V characteristic measurement was performed on the reference MOSFET. We confirmed that the ToGoFET probe could be operated at a gate voltage of 0 V due to channel ion implantation. The transconductance at the operating point (Vg = 0 V, Vd = 2 V) was 360 ㎂/V. After the fabrication process was completed, calibration was performed using a pure metal sample. For sensitivity calibration, the relationship between the input voltage of the sample and the output current of the probe was determined and the result was consistent with the measurement result of the reference MOSFET. An oxide sample measurement was performed as an example of an application of the new ToGoFET probe. According to the measurement, the ToGoFET probe could spatially resolve a hundred nanometers with a height of a few nanometers in both the topographic image and the ToGoFET image.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1463-1466
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• 1987

The problem of generating minimal area CMOS functional cell layout can be converted to that of decomposing the transistor connection graph into a minimum number of subgraphs, each having a pair of Euler paths with the same sequence of input labels on the N-graph and P-graph, which are portions of the graph corresponding to NMOS and PMOS parts respectively. This paper proposes a heuristic algorithm which yields a nearly minimal number of Euler paths from the path representation formula which represents the give a logic function. Subpath merging is done through a list processing scheme where the pair of paths which results in the lowest cost is successively merged from all candidate merge pairs until no further path merging and further reduction of number of subgraphs are possible. Two examples were shown where we were able to further reduce the number of interlaces, i.e., the number of non-butting diffusion islands, from 3 to 2, and from 2 to 1, compared to the earlier work [1].

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.3
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• pp.233-237
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• 2002

A giga-bit DRAM(dynamic random access memory) technology with W/WNx/poly-Si dual gate electrode is presented in 7his papers. We fabricated $0.16\mu\textrm{m}$ CMOS using this technology and succeeded in suppressing short-channel effects. The saturation current of nMOS and surface-channel pMOS(SC-pMOS) with a $0.16\mu\textrm{m}$ gate was observed 330 $\mu\A/\mu\textrm{m}$ and 100 $\mu\A/\mu\textrm{m}$ respectively. The lower salutation current of SC-pMOS is due to the p-doped poly gate depletion. SC-pMOS shows good DIBL(dram-induced harrier lowering) and sub-threshold characteristics, and there was no boron penetration.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.51-51
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• 2001

본 논문에서는 CMOS 로직과 pass-transistor logic(PTL)의 장점만을 가진 새로운 복합모드로직(Compound Mode Logic)을 제안하였다. 제안된 로직은 VLSI설계에서 중요하게 부각되고 있는 저전력, 고속 동작이 가능하며 실제로 전가산기를 설계하여 측정 한 결과 복합모드 로직의 power-delay 곱은 일반적인 CMOS로직에 비해 약 22% 개선되었다 제안한 복합모드 로직을 이용하여 고성능 32×32-bit 곱셈기를 설계 제작하였다. 본 논문의 곱셈기는 개선된 사인선택(Sign Select) Booth 인코더, 4-2 및 9-2 압축기로 구성된 데이터 압축 블록, 그리고 carry 생성 블록을 분리한 64-bit 조건 합 가산기로 구성되어 있다. 0.6um 1-poly 3-metal CMOS 공정을 이용하여 제작된 32×32-bit 곱셈기는 28,732개의 트랜지스터와 1.59×l.68 ㎜2의 면적을 가졌다. 측정 결과 32×32-bit 곱셈기의 곱셈시간은 9.8㎱ 이었으며, 3.3V 전원 전압에서 186㎽의 전력 소모를 하였다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.529-530
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• 2008

The proposed CMOS Quadrature VCO for WLAN application was designed in TSMC $0.18\;{\mu}m$ RF CMOS technology. The QVCO based on NMOS back-gate as a coupling transistor and switched capacitors array without tail transistors is designed to generate quadrature output signals. The simulated results show that the QVCO core consumed 3.67 mA and 6.6 mW from a 1.8 V supply. The QVCO is tunable between $4.76\;GHz\;{\sim}\;6.35\;GHz$ and has a phase noise lower than -116.8 ㏈c/Hz at 1 MHz offset over the entire tuning range