• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.202-207
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• 2010

In this paper, a novel voltage-controlled oscillator(VCO) using the open loop multiple split ring resonator(OLMSRR) is presented for improving the phase noise, implemented in 130 nm CMOS technology. Compared with the conventional CMOS LC resonator, the proposed CMOS OLMSRR has the larger coupling coefficient value, which makes a higher Q-factor, and has improved the phase noise of the VCO. The proposed CMOS VCO based OLMSRR has the phase noise of -99.67 dBc/Hz @ 1 MHz in the oscillation frequency. Compared with the VCO using the conventional CMOS LC resonator and the proposed VCO using the CMOS OLMSRR structure has been improved in 7 dB. The prototype 24 GHz CMOS VCO is implemented in 130 nm CMOS and occupies a compact die area of $0.7\;mm{\times}0.9\;mm$.

• Journal of electromagnetic engineering and science
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• v.9 no.1
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• pp.32-37
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• 2009

Various Class-E CMOS power amplifiers for GSM applications are presented. A stage-convertible transformer for a dual mode power amplifier is proposed to increase efficiency in the low-output power region. An integrated passive device(IPD) process is used to reduce combiner losses. A split secondary 1:2 transformer with IPD process is designed to obtain efficient and symmetric power combining. A quasi-four-pair structure of CMOS PA is also proposed to overcome the complexities of power combining.

• ETRI Journal
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• v.29 no.1
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• pp.70-78
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• 2007

A new low-voltage CMOS interface circuit with digital output for piezo-resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo-resistance due to applied pressure and to allow low-voltage circuit operation. A simple 1-bit first-order delta-sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 ${\mu}m$ CMOS technology and draws less than 200 ${\mu}A$ from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non-linearity error.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.247-255
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• 2011

This paper describes a CMOS outphasing transmitter using two wideband phase modulators. The proposed architecture can simplify the overall outphasing transmitter architecture using two-point phase modulation in phase-locked loop, which eliminates the necessity digital-to-analog converters, filters, and mixers. This architecture is verified with a WCDMA signal at 1.65 GHz. The prototype is fabricated in standard 130 nm CMOS technology. The measurement results satisfied the spectrum mask and 4.9% EVM performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.687-694
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• 2016

A differential power amplifier operating at millimeter-wave frequencies is demonstrated using a 65-nm CMOS technology. All of the input, output, and inter-stage network are implemented by transformers only, enabling impedance matching with low loss and a wide bandwidth. The millimeter-wave power amplifier exhibits measured small-signal gain exceeding 12.6 dB over a 3-dB bandwidth from 45 to 56 GHz. The output power and PAE are 13 dBm and 11.7%, respectively at 50 GHz.

• Proceedings of the Materials Research Society of Korea Conference
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• 2008.05a
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• pp.3.2-3.2
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• 2008

• Journal of the Korean Society for Precision Engineering
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• v.20 no.5
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.60-68
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• 2000

This paper describes a design methodology for the CMOS current source which can be implemented in standard memory process. The proposed techniques provide a good characteristic against the power-supply variation by utilizing a self-bias circuit and the reduction of the first-order component of the temperature variation through the new temperature compensation technique and include a new current-sensing start-up circuit enabling a robust operation against the voltage noise generated during the operation of the chip. In addition to the circuit-design technology, techniques where the proposed CMOS current-reference circuit can be applied to the clocking circuits of a very high-speed DRAM are presented. The feasibility of the suggested design methodology for the CMOS current reference is demonstrated by both the analytical method and the circuit simulation.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.197-200
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• 2000

This paper proposes a CMOS low noise VGA. It describes the noise optimization method of the proposed VGA. The designed VGA provides of a 0 to 21.30dB gain variation and its bandwidth of 49MHz. The input reflected noise voltage is 4.84nV/sqrt-hz at 1MHz and noise figure is 14.53dB(Rs=50 Ω). The VGA was fabricated using a 0.35-${\mu}{\textrm}{m}$ CMOS technology.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.545-546
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• 2008

This paper presents a low power CMOS low noise amplifier for UWB applications. To reduce the power consumption, two cascode amplifiers was stacked in DC. Designed with $0.18-{\mu}m$ CMOS technology, the proposed LNA achieves 20dB flat gain, below 3dB noise figure, and the power consumption of 5.2mW from a 1.8 V supply voltage.