• Journal of the Korea Society for Simulation
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• v.17 no.4
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• pp.199-208
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• 2008

Lately, since Complementary Metal Oxide Semiconductor(CMOS) image sensor system has low power, low cost and been miniaturized, hardware and applied software studies using these strengths are being carrying on actively. However, the products equipped with CMOS image sensor based polling method yet has several problems in degree of completeness of applied software and firmware, compared with hardware’s. CMOS image sensor system has an ineffective synchronous problem due to superfluous message exchange. Also when a sending of data is delayed continually, overhead of re-sending is large. So because of these, it has a problem in structural stability according to Polling Method. In this study, polling cycle was subdivided in high-speed synchronization method of firmware -based through MCU and synchronization method of Stepwise was proposed. Also, re-connection and data sending were advanced more efficiently by using interrupt way. In conclusion, the proposed method showed more than 20 times better performance in synchronization time and error connection. Also, a board was created by using C328R board of CMOS image sensor-based and ATmega128L which has low power, MCU and camera modules of proposed firmware were compared with provided software and analyzed in synchronization time and error connection.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.50-57
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• 2008

In this paper, a high-efficiency charge pump for use in CMOS image sensor(CIS) is proposed. The proposed charge pump pursues high pumping efficiency by minimizing the switching and reversion losses by taking advantage of operation characteristics of CIS. That is, the proposed charge pump minimizes the switching loss by dynamically controlling the size of clock driver, pumping capacitor, and charge transfer switch based on the operation phase of CIS pixel sensor. The charge pump also minimizes the reversion loss by guaranteeing a sufficient non-overlapping period of local clocks using a tri-state local clock driver adapting the schmitt trigger. Comparison results using a 0.13-um CMOS process technology indicate that the proposed charge pump achieves up to 49.1% reduction on power consumption under no loading current condition as compared to conventional charge pump. They also indicate that the charge pump provides 19.0% reduction on power consumption under the maximum loading current condition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.20-27
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• 2011

A CMOS Image Sensor(CIS) mounted on mobile appliances always needs a low power consumption because of the battery life cycle. In this paper, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination, a low power single slope A/D converter with a novel comparator, and etc. Based on 0.13um CMOS process, the chip satisfies QVGA resolution($320{\times}240$ pixels) whose pitch is 2.25um and whose structure is 4-Tr active pixel sensor. From the experimental results, the ADC in the middle of CIS has a 10-b resolution, the operating speed of CIS is 16 frame/s, and the power dissipation is 25mW at 3.3V(Analog)/1.8V(Digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption is reduced approximately by 22% in sleep mode, 20% in operating mode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.38-43
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• 2006

In this paper, we propose the efficient dead pixel detection algorithm for CMOS image sensors and its hardware architecture. The CMOS image sensors as image input devices are becoming popular due to the demand for miniaturized, low-power and cost-effective imaging systems. However, the presence of the dead pixels degrade the image quality. To detect the dead pixels, the proposed algorithm is composed of scan, trace and detection step. The experimental results showed that it could detect 99.99% of dead pixels. It was designed in a hardware description language and total logic gate count is 3.2k using 0.25 CMOS standard cell library.

• Journal of IKEEE
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• v.24 no.4
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• pp.942-949
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• 2020

In this paper, we propose an improved algorithmic ADC for CMOS Image Sensor that is suitable for a column-parallel readout circuit. The algorithm of the conventional algorithmic ADC is modified so that it can operate as a single amplifier while being independent of the capacitor ratio and insensitive to the gain of the op-amp, and it has a high conversion efficiency by using an adaptive biasing amplifier. The proposed ADC is designed with 0.18-um Magnachip CMOS process, Spectre simulation shows that the power consumption per conversion speed is reduced by 37% compared with the conventional algorithmic ADC.

• International Journal of Aeronautical and Space Sciences
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• v.13 no.2
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• pp.260-265
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• 2012

Satellite devices for fine attitude control of the Science & Technology Satellite-2 (STSAT-2). Based on the mission requirements of STSAT-2, the conventional analog-type sun sensors were found to be inadequate, motivating the development of a compact, fast and fine digital sun sensor (FDSS). The FDSS uses a CMOS image sensor and has an accuracy of less than 0.03degrees, an update rate of 5Hz and a weight of less than 800g. A pinhole-type aperture is substituted for the optical lens to minimize its weight. The target process speed is obtained by utilizing the Field Programmable Gate Array (FPGA), which acquires images from the CMOS sensor, and stores and processes the image data. The sensor accuracy is maintained by a rigorous centroid algorithm. This paper describes the FDSS designs, realizations, tests and calibration results.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.131-136
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• 2015

This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitor and feedback structure. The designed circuit has been fabricated by using $0.18{\mu}m$ 1-poly 6-metal standard CMOS technology. This sensor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposed pixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity in high light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. The capacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed structure, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results demonstrate wide dynamic range feature of the proposed PPS.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.809-813
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• 2004

In this paper, we developed a network camera for CMOS camera module inspection. The design, implementation details including embedded linux porting and CPLD logics, and performance of network camera are described. The network camera consists of SoC(S3C4530A), CPLD and CMOS image sensor. In order to image data of CMOS image sensor we designed capture logics on CPLD by using VHDL program. Embedded Linux such as uClinux is performed on the network camera to utilize development environment and TCP/IP protocol specification. The application is based on socket communication between GUI on PC and Embedded Linux based network camera. When JPEG compression is applied, the transmission speed was improved enough for this system to be used for an alternative of expensive CCTV or remote monitoring system in a power plant and uninhabited places.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.270-274
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• 2008

This paper proposes an advanced signal processing circuit for a fingerprint sensor based on ridge resistivity. A novel fingerprint integrated sensor using ridge resistivity variation resulting from ridges and valleys on the fingertip is presented. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. The sensor circuit blocks were designed and simulated in a standard CMOS 0.35 ${\mu}m$ process.

• Journal of Astronomy and Space Sciences
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• v.18 no.3
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• pp.231-238
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• 2001

A prototype CMOS (complementary metal oxide semiconductor) imaging system has been built and the possibility of applying to the application to astronomical observations has been investigated. The CCD (charge coupled device) image sensor has been the mainstay of image capture and astronomical imaging for the last 30 years, but CMOS devices have shown rapidly increasing success and have been adapted to many commercial imaging systems . Although the photometric performances and system noise of CMOS sensors are lower than that of CCD image sensors, CMOS Imaging system can be used to obtain general image capture for astronomical applications.