• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.47-53
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• 2004

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are composed with ternary voltage mode NMAX, NMIN, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.35um CMOS technology and 3.3Volts supply voltage. The architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.371-374
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• 1998

본 논문에서는 muller법과 regular falsi법에 의한 CMOS 반전 증폭 회로를 해석하는 방법을 제안한다. Muller법과 regular falsi법을 이용하여 회로의 절점전압과 branch 전류를 예측하였고 회로의 출력 절점에서 KCL을 만족하도록 하였다. CMOS 반전 증폭 회로의 모의실험을 수행한 결과 MEDICI에 사용된 결합법에 비해 전압특성과 전류특성은 각각 5%와 5.4%의 최대상대오차를 보였다.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.841-844
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• 2005

Multi-output VC-TCXO (Voltage Controlled-Temperature Compensated Crystal Oscillator) for WCDMA has integrated the additional CMOS inverter, so it can be normal clipped sinewave output and additional CMOS output and it can be satisfied the VC-TCXO Characteristics that WCDMA system required. In this paper, however 26MHz is used for reference frequency, similarly and practically, it is usable from 10MHz to 40MHz, Most important factor to integrate CMOS inverter internally is the isolation between normal output and additional output. For this, it is separated in package design, due to this, when it isn't used additional output, it shows the same electrical performance, when it is used additional output, it has minimum-rized the interference. and then the important characteristics in reference oscillator are met to WCDMA system's requirements, like phase noise and frequency short term stability.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.17.2-17.2
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• 2010

Printed electronics is an emerging technology to realize various microelectronic devices via a cost-effective method. Here we demonstrated a high performance of p-channel and n-channel top-gate/bottom contact polymer field-effect transistors (FETs), and applications to elementary organic complementary inverter and ring oscillator circuits by inkjet processing. We could obtained high field-effect mobility more than $0.4\;cm^2/Vs$ for both of p-channel and n-channel FETs, and successfully measured inkjet-printed polymer inverters. The performance of devices highly depends on the selection of dielectrics, printing condition and device architecture. Optimized CMOS ring oscillators with p-type and n-type polymer transistors showed as high as 50 kHz operation frequency. This research was financially supported by development of next generation RFID technology for item level applications (2008-F052-01) funded by the ministry of knowledge economy (MKE).

• Journal of Information Display
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• v.6 no.4
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• pp.11-15
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• 2005

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.118-119
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• 2007

High performance three-dimensional (3-D) stacked poly-Si complementary metal-oxide semiconductor (CMOS) inverters with a high quality laser crystallized channel were fabricated. Low temperature crystallization methods of a-Si film using the excimer-laser annealing (ELA) and sequential lateral solidification (SLS) were performed. The NMOS thin-film-transistor (TFT) at lower layer of CMOS was fabricated on oxidized bulk Si substrate, and the PMOS TFT at upper layer of CMOS was fabricated on interlayer dielectric film. The 3-D stacked poly-Si CMOS inverter showed excellent electrical characteristics and was enough for the vertical integrated CMOS applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.1-9
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• 2006

In this paper, a couple of 10Gb/s transimpedance amplifiers are realized in a 0.18um standard CMOS technology for optical communication applications. First, the voltage-mode inverter TIA(I-TIA) exploits inverter input configuration to achieve larger effective gm, thus reducing the input impedance and increasing the bandwidth. I-TIA demonstrates $56dB{\Omega}$ transimpedance gain, 14GHz bandwidth for 0.25pF photodiode capacitance, and -16.5dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. However, both its inherent parasitic capacitance and the package parasitics deteriorate the bandwidth significantly, thus mandating very judicious circuit design. Meanwhile, the current-mode RGC TIA incorporates the regulated cascade input configuration, and thus isolates the large input parasitic capacitance from the bandwidth determination more effectively than the voltage-mode TIA. Also, the parasitic components give much less impact on its bandwidth. RGC TIA provides $60dB{\Omega}$ transimpedance gain, 10GHz bandwidth for 0.25pF photodiode capacitance, and -15.7dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. Main drawback is the power dissipation which is 4.5 times larger than the I-TIA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.9-14
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• 2009

In this paper, we proposed a novel OTP unit bit of CMOS gate oxide antifuse using the standard CMOS process without additional process. The proposed OTP unit bit is composed of 3 transistors including an NMOS gate oxide antifuse and a sense amplifier of inverter type. The layout area of the proposed OTP unit bit is $22{\mu}m^2$ similar to a conventional OTP unit bit. The programming time of the proposed OTP unit bit is 3.6msec that is improved than that of the conventional OTP unit bit because it doesn't use high voltage blocking elements such as high voltage blocking switch transistor and resistor. And the OTP array with the proposed OTP unit bit doesn't need sense amplifier and bias generation circuit that are used in a conventional OTP array because sense amplifier of inverter type is included to the proposed OTP unit bit.

• Journal of Sensor Science and Technology
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• v.3 no.3
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• pp.16-21
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• 1994

A 3-terminal pin-type photosensor with gate contrail is fabricated using standard silicon CMOS IC process. The photosensor of a $100{\mu}m{\times}120{\mu}m$ size has dark current less than 1nA and its breakdown voltage is -14V with a depletion capacitance 0.75 pF at -5V reverse bias. Responsivity at 0V gate voltage is 0.25A/W at $0.633{\mu}m$ wavelength, 0.19A/W at $0.805{\mu}m$. Responsivity increases with increasing gate voltage. The integrated circuit of photosensor and CMOS inverter shows $22K{\Omega}$ transimpedance and photocurrent of $90{\mu}A$ switchs the output state of digital inverter without additional amplifier.

• Journal of IKEEE
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• v.23 no.2
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• pp.681-686
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• 2019

This paper proposes a CMOS temperature sensor using inverter delay chains of the same size based on the pulse shrinking method. A temperature-pulse converter (TPC) uses two different temperature delay lines with inverter chains to generate a pulse in proportion to temperature, and a time-digital converter (TDC) shrinks the pulse using inverter chains of the same size to convert pulse width into a digital value to be insensitive to process changes. The chip was implemented with a $0.49{\mu}m{\times}0.23{\mu}m$ area using a $0.35{\mu}m$ CMOS process with a supply voltage of 3.3V. The measurement results show a resolution of $0.24^{\circ}C/bit$ for 9-bit data for a temperature sensor range of $0^{\circ}C$ to $100^{\circ}C$.