• Title/Summary/Keyword: CMOS integrated circuit

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Accurate Equation Analysis for RF Negative Resistance circuit at High Frequency Operation Range (고주파수 영역의 정확도 높은 RF 부성저항 회로 분석)

  • Yun, Eun-Seung;Hong, Jong-Phil
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.4
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    • pp.88-95
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    • 2015
  • This paper presents a new analysis of RF negative resistance (RFNR) circuits, known as a negative resistance generator. For accurate equation analysis of RFNR, this study examined the effects of the gate resistance and the source parasitic capacitance of the transistor. In addition, the input admittance of the conventional equation was calculated by looking into the source-terminal of the transistor, whereas that of the proposed equation was calculated by examining the gate-terminal of the transistor. The proposed equation analysis is more accurate than that of the conventional analysis, especially for higher frequency range. This paper verify the accuracy of the proposed analysis at high frequency range using the simulation.

Hands-On Experience-Based Comprehensive Curriculum for Microelectronics Manufacturing Engineering Education

  • Ha, Taemin;Hong, Sang Jeen
    • Transactions on Electrical and Electronic Materials
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    • v.17 no.5
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    • pp.280-288
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    • 2016
  • Microelectronic product consumers may already be expecting another paradigm shift with smarter phones over smart phones, but the current status of microelectronic manufacturing engineering education (MMEE) in universities hardly makes up the pace for such a fast moving technology paradigm shift. The purpose of MMEE is to educate four-year university graduates to work in the microelectronics industry with up-to-date knowledge and self-motivation. In this paper, we present a comprehensive curriculum for a four-year university degree program in the area of microelectronics manufacturing. Three hands-on experienced-based courses are proposed, along with a methodology for undergraduate students to acquire hands-on experience, towards integrated circuits (ICs) design, fabrication and packaging, are presented in consideration of manufacturing engineering education. Semiconductor device and circuit design course for junior level is designed to cover how designed circuits progress to micro-fabrication by practicing full customization of the layout of digital circuits. Hands-on experienced-based semiconductor fabrication courses are composed to enhance students’ motivation to participate in self-motivated semiconductor fab activities by performing a series of collaborations. Finally, the Microelectronics Packaging course provides greater possibilities of mastered skillsets in the area of microelectronics manufacturing with the fabrication of printed circuit boards (PCBs) and board level assembly for microprocessor applications. The evaluation of the presented comprehensive curriculum was performed with a students’ survey. All the students responded with “Strongly Agree” or “Agree” for the manufacturing related courses. Through the development and application of the presented curriculum for the past six years, we are convinced that students’ confidence in obtaining their desired jobs or choosing higher degrees in the area of microelectronics manufacturing was increased. We confirmed that the hypothesis on the inclusion of handson experience-based courses for MMEE is beneficial to enhancing the motivation for learning.

A Fully Integrated SoC for Smart Capsule Providing In-Body Continuous pH and Temperature Monitoring

  • Liu, Heng;Jiang, Hanjun;Xia, Jingpei;Chi, Zhexiang;Li, Fule;Wang, Zhihua
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.5
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    • pp.542-549
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    • 2016
  • This paper presents a SoC (System-on-a-Chip) dedicated for a single-chip smart capsule which can be used to continuously monitor human alimentary canal pH and temperature values. The SoC is composed of the pH and temperature sensor interface circuit, a wireless transceiver, the power management circuit and the flow control logic. Fabricated in $0.18{\mu}m$ standard CMOS technology, the SoC occupies a die area of ${\sim}9 mm^2$. The SoC consumes 6.15 mW from a 3 V power supply, guaranteeing the smart capsule battery life is no less than 24 hours when using 50 mAh coin batteries. The experimental results show that measurement accuracy of the smart capsule is ${\pm}0.1$ pH and ${\pm}0.2^{\circ}C$ for pH and temperature sensing, respectively, which meets the requirement of in-body pH and temperature monitoring in clinical practice.

5.0 inch WVGA Top Emission AMOLED Display for PDA

  • Lee, Kwan-Hee;Ryu, Seoung-Yoon;Park, Sang-Il;Ryu, Do-Hyung;Kim, Hun;Song, Seung-Yong;Chung, Bo-Yong;Park, Yong-Sung;Kang, Tae-Wook;Kim, Sang-Chul;Cho, Yu-Sung;Park, Jin-Woo;Kwon, Jang-Hyuk;Chung, Ho-Kyoon
    • 한국정보디스플레이학회:학술대회논문집
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    • 2003.07a
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    • pp.7-10
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    • 2003
  • Samsung SDI has developed a full color 5.0" WVGA AMOLED display with top emission and a super fine pitch of 0.1365mm(l86ppi), the world's highest resolution OLED display ever reported to date. Scan driver circuits and demux circuit were integrated into the display panel, using low temperature poly-Si TFT CMOS technology, and data driver circuit were mounted using COG chips. Peak luminescence was greater than 300cd/ $m^2$ with power consumption of 500mW with 30% of the pixels on illuminated.

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E-band low-noise amplifier MMIC with impedance-controllable filter using SiGe 130-nm BiCMOS technology

  • Chang, Woojin;Lee, Jong-Min;Kim, Seong-Il;Lee, Sang-Heung;Kang, Dong Min
    • ETRI Journal
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    • v.42 no.5
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    • pp.781-789
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    • 2020
  • In this study, an E-band low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) has been designed using silicon-germanium 130-nm bipolar complementary metal-oxide-semiconductor technology to suppress unwanted signal gain outside operating frequencies and improve the signal gain and noise figures at operating frequencies. The proposed impedance-controllable filter has series (Rs) and parallel (Rp) resistors instead of a conventional inductor-capacitor (L-C) filter without any resistor in an interstage matching circuit. Using the impedance-controllable filter instead of the conventional L-C filter, the unwanted high signal gains of the designed E-band LNA at frequencies of 54 GHz to 57 GHz are suppressed by 8 dB to 12 dB from 24 dB to 26 dB to 12 dB to 18 dB. The small-signal gain S21 at the operating frequencies of 70 GHz to 95 GHz are only decreased by 1.4 dB to 2.4 dB from 21.6 dB to 25.4 dB to 19.2 dB to 24.0 dB. The fabricated E-band LNA MMIC with the proposed filter has a measured S21 of 16 dB to 21 dB, input matching (S11) of -14 dB to -5 dB, and output matching (S22) of -19 dB to -4 dB at E-band operating frequencies of 70 GHz to 95 GHz.

Performance Analysis of Adaptive Bandwidth PLL According to Board Design (보드 설계에 따른 Adaptive Bandwidth PLL의 성능 분석)

  • Son, Young-Sang;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.146-153
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    • 2008
  • In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

Highly power-efficient and reliable light-emitting diode backlight driver IC for the uniform current driving of medium-sized liquid crystal displays

  • Hong, Seok-In;Nam, Ki-Soo;Jung, Young-Ho;Ahn, Hyun-A;In, Hai-Jung;Kwon, Oh-Kyong
    • Journal of Information Display
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    • v.13 no.2
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    • pp.73-82
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    • 2012
  • In this paper, a light-emitting diode (LED) backlight driver integrated circuit (IC) for medium-sized liquid crystal displays (LCDs) is proposed. In the proposed IC, a linear current regulator with matched internal resistors and an adaptive phase-shifted pulse-width modulation (PWM) dimming controller are also proposed to improve LED current uniformity and reliability. The double feedback loop control boost converter is used to achieve high power efficiency, fast transient characteristic, and high dimming frequency and resolution. The proposed IC was fabricated using the 0.35 ${\mu}m$ bipolar-CMOS-DMOS (BCD) process. The LED current uniformity and LED fault immunity of the proposed IC were verified through experiments. The measured power efficiency was 90%; the measured LED current uniformity, 97%; and the measured rising and falling times of the LED current, 86 and 7 ns, respectively. Due to the fast rising and falling characteristics, the proposed IC operates up to 39 kHz PWM dimming frequency, with an 8-bit dimming resolution. It was verified that the phase difference between the PWM dimming signals is changed adaptively when LED fault occurs. The experiment results showed that the proposed IC meets the requirements for the LED backlight driver IC for medium-sized LCDs.

AE32000B: a Fully Synthesizable 32-Bit Embedded Microprocessor Core

  • Kim, Hyun-Gyu;Jung, Dae-Young;Jung, Hyun-Sup;Choi, Young-Min;Han, Jung-Su;Min, Byung-Gueon;Oh, Hyeong-Cheol
    • ETRI Journal
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    • v.25 no.5
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    • pp.337-344
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    • 2003
  • In this paper, we introduce a fully synthesizable 32-bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35-${\mu}m$ library and a 0.18-${\mu}m$ library. With the 0.35-${\mu}m$ library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18-${\mu}m$ library.

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Design of 77 GHz Automotive Radar System (77 GHz 차량용 레이더 시스템 설계)

  • Nam, Hyeong-Ki;Kang, Hyun-Sang;Song, Ui-Jong;Cui, Chenglin;Kim, Seong-Kyun;Nam, Sang-Wook;Kim, Byung-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.9
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    • pp.936-943
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    • 2013
  • This work presents the design and measured results of the single channel automotive radar system for 76.5~77 GHz long range FMCW radar applications. The transmitter uses a commercial GaAs monolithic microwave integrated circuit(MMIC) and the receiver uses the down converter designed using 65 nm CMOS process. The output power of the transmitter is 10 dBm. The down converter chip can operate at low LO power as -8 dBm which is easily supplied from the transmitter output using a coupled line coupler. All MMICs are mounted on an aluminum jig which embeds the WR-10 waveguide. A microstrip to waveguide transition is designed to feed the embedded waveguide and finally high gain horn antennas. The overall size of the fabricated radar system is $80mm{\times}61mm{\times}21mm$. The radar system achieved an output power of 10 dBm, phase noise of -94 dBc/Hz at 1 MHz offset and a conversion gain of 12 dB.

Design and Hardware Implementation of High-Speed Variable-Length RSA Cryptosystem (가변길이 고속 RSA 암호시스템의 설계 및 하드웨어 구현)

  • 박진영;서영호;김동욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.9C
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    • pp.861-870
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    • 2002
  • In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.