• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.191-194
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• 2007

The paper clarifies all the noise sources of a CMOS image sensor, with which the GOCI (Geostationary Ocean Color Imager) is equipped, and analyzes their contribution to a nonlinear image sensor model. In particular, the noise PDF (Probability Density Function) is derived in terms of sensor-gain coefficients: a linear and a nonlinear gains. As a result, the relation between the noise characteristic and the sensor gains is studied.

• Current Optics and Photonics
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• v.7 no.5
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• pp.485-495
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• 2023

The pixel size in high-resolution complementary metal-oxide-semiconductor (CMOS) image sensors continues to shrink due to chip size limitations. However, the pixel pitch's miniaturization causes deterioration of optical performance. As one solution, a quad color filter (CF) array with pixel binning has been developed to enhance sensitivity. For high sensitivity, the microlens structure also needs to be optimized as the CF arrays change. In this paper, the covered microlens, which consist of four microlenses covered by one large microlens, are proposed for the quad CF array in the backside illumination pixel structure. To evaluate the optical performance, the suggested microlens structure was simulated from 0.5 ㎛ to 1.0 ㎛ pixels at the center and edge of the sensors. Moreover, all pixel structures were compared with and without in-pixel deep trench isolation (DTI), which works to distribute incident light uniformly into each photodiode. The suggested structure was evaluated with an optical simulation using the finite-difference time-domain method for numerical analysis of the optical characteristics. Compared to the conventional microlens, the suggested microlens show 29.1% and 33.9% maximum enhancement of sensitivity at the center and edge of the sensor, respectively. Therefore, the covered microlens demonstrated the highly sensitive image sensor with a quad CF array.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.1
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• pp.17-22
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• 2001

The floating-gate MOSFETs were fabricated by employing 1.5 m n-well CMOS process and their optical-electrical properties were characterized for the application to CMOS image sensor system. Based on the simulation of energy band diagram and operating mechanism of parasitic BJT were proposed as solutions for the increase of photo-current value. In order to realize them, MOSFETs having multi-gate and channel structures were fabricated and 60% increase in photo-current was achieved through enlargement of depletion layer and parallel connection of parasitic BJTs by channel division.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.79-82
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• 2015

This paper proposes a novel complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) and presents its performance characteristics. The proposed APS exhibits a linear-logarithmic response, which is simulated using a standard $0.35-{\mu}m$ CMOS process. To maintain high sensitivity and improve the dynamic range (DR) of the proposed APS at low and high-intensity light, respectively, two additional nMOSFETs are integrated into the structure of the proposed APS, along with a photogate. The applied photogate voltage reduces the sensitivity of the proposed APS in the linear response regime. Thus, the conversion gain of the proposed APS changes from high to low owing to the addition of the capacitance of the photogate to that of the sensing node. Under high-intensity light, the integrated MOSFETs serve as voltage-light dependent active loads and are responsible for logarithmic compression. The DR of the proposed APS can be improved on the basis of the logarithmic response. Furthermore, the reference voltages enable the tuning of the sensitivity of the photodetector, as well as the DR of the APS.

• Journal of Sensor Science and Technology
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• v.19 no.4
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• pp.285-290
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• 2010

In this paper, a dynamic range(DR) extension technique based on a 3-transistor active pixel sensor(APS) and dual image sampling is proposed. The feature of the proposed APS is that the APS uses two or more photodiodes with different sensitivities, such as a high-sensitivity photodiode and a low-sensitivity photodiode. Compared with previously proposed wide DR(WDR) APS, the proposed approach has several advantages, such as no-external equipments or signal processing, no-additional time-requirement for additional charge accumulation, simple operation and adjustable DR extension by controlling parasitic capacitance and sensitivity of two photodiodes. Approximately 16 dB of DR extension was evaluated from the simulation for the situation of 10 times of sensitivity difference and the same size of parasitic capacitance between those two photodiodes.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1680-1681
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• 2011

In this paper, particle counting system using a CMOS image sensor is demonstrated. The system utilizes a linear photodetector array as a detection element. Therefore, the particles are detected by large detection region, in contrast to a single detector in conventional particle counting devices, while maintaining the sensitivity. The advantage of proposed system is that particles are detected in a relatively large area without using the particle focusing method. Also, proposed system can be easily integrated with a microfluidic chip by attaching the device underneath the bottom plate of the microfluidic chip. Detection of polystyrene microbeads has been tested at a flow rate of 4.89mm/s. For 21 measurements, proposed system showed an average count error of 7.29% and a standard deviation of 4.74%. Potentially, the proposed system can detect even smaller particles simply by utilizing a higher resolution CMOS image sensor.

• The Journal of the Korea Contents Association
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• v.13 no.10
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• pp.54-61
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• 2013

This paper presents a simplified hardware based edge detection circuit which is based on an analog correlator combining with the neighbor pixels in CMOS image sensor. A pixel element of the edge detector consists of an active pixel sensor and an analog correlator circuit which connects two neighbor pixels. The edge detector shares a comparator on each column that the comparator decides an edge of the target pixel with an adjustable reference voltage. The circuit detects image edge from CIS directly that reduces area and power consumption 4 times and 20%, respectively, compared with the previous works. And also it has advantage to regulate sensitivity of the edge detection because the threshold value is able to control externally. The fabricated chip has 34% of fill factor and 0.9 ${\mu}W$ of power per a pixel under 0.18 ${\mu}m$ CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.59-64
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• 2006

The slope of the ramp generator in a single slope ADC(analog-to-digital converter) suffers from process and frequency variation. This variation in ramp slope causes ADC gain variation and eventually limits the performance of the ISP(image signal processing) in a CIS(CMOS image sensor) that uses the single slope ADC. This paper proposes a ramp slope BISC(built-in-self-calibration) scheme for CIS. The CIS with proposed BISC was fabricated with a $0.35{\mu}m$ process. The measurement results show that the proposed architecture effectively calibrate the ramp slope against process and clock frequency variation. The silicon area overhead is less than $0.7\%$ of the full chip area.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1787-1790
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• 2005

We have developed satellite devices for fine attitude control of the Science & Technology Satellite-2 (STSAT-2) scheduled to be launched in 2007. The analog sun sensors which have been continuously developed since the 1990s are not adequate for satellites which require fine attitude control system. From the mission requirements of STSAT-2, a compact, fast and fine digital sensor was proposed. The test of the fine attitude determination for the pitch and roll axis, though the main mission of STSAT-2, will be performed by the newly developed FDSS. The FDSS use a CMOS image sensor and has an accuracy of less than 0.01degrees, an update rate of 20Hz and a weight of less than 800g. A pinhole-type aperture is substituted for the optical lens to minimize the weight while maintaining sensor accuracy by a rigorous centroid algorithm. The target process speed is obtained by utilizing the Field Programmable Gate Array (FPGA) in acquiring images from the CMOS sensor, and storing and processing the data. This paper also describes the analysis of the optical performance for the proper aperture selection and the most effective centroid algorithm.