• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.34-41
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• 2011

This paper presents a 24 channel capacitive touch sensing ASIC. This ASIC consists of analog circuit part and digital circuit part. Analog circuits convert user screen touch into electrical signal and digital circuits represent this signal change as digital data. Digital circuit also has an I2C interface for operation parameter reconfiguration from host machine. This interface guarantees the stable operation of the ASIC even against wide operation condition change. This chip is implemented with 0.18 um CMOS process. Its area is about 3 $mm^2$ and power consumption is 5.3mW. A number of EDA tools from Cadence and Synopsys are used for chip design.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.55-63
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• 1999

A new CMOS If Package design methodology is presented, analyzing the electrical characteristics of a package and its effects on the CMOS digital circuits. An analytical investigation of the package noise effects due to the simultaneous switching of the gates within a chip, i.e., simultaneous switching noise (SSN) is performed. Then not only are novel design formula to meet electrical constraints of the Package derived, but also package design methodology based on the formula is proposed. Further, in order to demonstrate the Proposed design methodology, the design results are compared with HSPICE (a general purpose circuit simulator) simulation for $0.3\mu\textrm{m}$-based CMOS circuits. According to the proposed design procedures, it is shown that the results have excellent agreements with those of HSPICE simulation.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.537-540
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• 2004

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation. we present an Interpolation type architecture. In order to overcome the problems of high speed operation further a novel encoder, a circuit for the Reference Fluctuation, an Averaging Resistor and a Track & Hold for the improved SNR are proposed. The proposed Interpolation ADC consists of Track & Holt four resistive ladders with 64 taps, 32 comparators and digital blocks. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply.

• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.54-60
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• 1994

In this paper, the multi-sensor signal processing IC is designed. It consists of an analog multiplexer for selection of multi-sensor signals, active filters for noise rejection and signal amplification, and a sample and hold circuit for interface with digital signal processing. By implementing these circuits with CMOS transistors, integration, low power dissipation and miniaturization of the total signal processing system have been made possible.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.518-521
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• 1998

This paper describes a 3.3V-65MHz 12BIT CMOS current-mode DAC designed with a 8 MSB current matirx stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch ahs been employed. The simulation results of the designed DAC show a coversion rate of 65MHz, a powr dissipation of 71.7mW, a DNL of .+-.0.2LSB and an INL of .+-.0.8LSB with a single powr supply of 3.3V for a CMOS 0.6.mu.m n-well technology.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• Journal of Sensor Science and Technology
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• v.3 no.3
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• pp.16-21
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• 1994

A 3-terminal pin-type photosensor with gate contrail is fabricated using standard silicon CMOS IC process. The photosensor of a $100{\mu}m{\times}120{\mu}m$ size has dark current less than 1nA and its breakdown voltage is -14V with a depletion capacitance 0.75 pF at -5V reverse bias. Responsivity at 0V gate voltage is 0.25A/W at $0.633{\mu}m$ wavelength, 0.19A/W at $0.805{\mu}m$. Responsivity increases with increasing gate voltage. The integrated circuit of photosensor and CMOS inverter shows $22K{\Omega}$ transimpedance and photocurrent of $90{\mu}A$ switchs the output state of digital inverter without additional amplifier.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.187-191
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• 2007

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.691-698
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• 2008

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7\;LSB$, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.