• Transactions on Electrical and Electronic Materials
• /
• v.5 no.2
• /
• pp.71-75
• /
• 2004

This paper proposes a new bandgap reference (BGR) circuit which takes advantage of a cascode current mirror biasing to reduce the V$\_$ref/ variation, and sizing technique, which utilizes two related ratio numbers k and N, to reduce the PNP BJT area. The proposed BGR is designed and fabricated on a test chip with a goal to provide a reference voltage to the 10 bit A/D(4-4-4 pipeline architecture) converter of the CMOS Active Pixel Sensor (APS) imager to be used in X-ray imaging. The basic temperature variation effect on V$\_$ref/ of the BGR has a maximum delta of 6 mV over the temperature range of 25$^{\circ}C$ to 70$^{\circ}C$. To verify that the proposed BGR has radiation hardness for the X-ray imaging application, total ionization dose (TID) effect under Co-60 exposure conditions has been evaluated. The measured V$\_$ref/ variation under the radiation condition has a maximum delta of 33 mV over the range of 0 krad to 100 krad. For the given voltage, temperature, and radiation, the BGR has been satisfied well within the requirement of the target 10 bit A/D converter.

• Journal of Sensor Science and Technology
• /
• v.23 no.5
• /
• pp.332-336
• /
• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.

• Journal of Sensor Science and Technology
• /
• v.18 no.4
• /
• pp.274-279
• /
• 2009

In this paper, a wide dynamic range active pixel sensor(APS) with output voltage feedback structure has been designed by a 2-poly 4-metal 0.35 $\mu$m standard CMOS technology. We presented a novel APS with output voltage feedback, which exhibits a wide dynamic range. The dynamic range increases at the cost of an additional diode and an additional MOSFET. The output voltage feedback structure enables the control of the output voltage level by itself, as incident light power varies. It is confirmed that the light level which the output voltage level of proposed APS is saturated is about 120,000 lux, which is higher than that of a conventional 3-transistor APS.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.149-156
• /
• 2013

This paper presents a hardware edge detector of image signal at pixel level of CMOS image sensor (CIS). The circuit detects edges of an image based on a bump circuit combining with the pixels. The APS converts light into electrical signals and the bump circuit compares the brightness between the target pixel and its neighbor pixels. Each column on CIS 64 by 64 pixels array shares a comparator. The comparator decides a peak level of the target pixel comparing with a reference voltage. The proposed edge detector is implemented using 0.18um CMOS technology. The circuit shows higher fill factor 34% and power dissipation by 0.9uW per pixel at 1.8V supply.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.2
• /
• pp.104-110
• /
• 2011

A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.

• Proceedings of the IEEK Conference
• /
• 2004.08c
• /
• pp.482-485
• /
• 2004

We fabricated a hybrid bulk/fully depleted silicon on insulator (FDSOI) complementary metal oxide semiconductor (CMOS) active pixel image sensor. The active pixel is comprised of reset and source follower transistors on the SOI seed wafer, while the pinned photodiode and readout gate and floating diffusion are fabricated on the SOI handle wafer after the removal of the buried oxide. The source of dark current is eliminated by hybrid bulk/FDSOI pixel structure between localized oxidation of silicon (LOCOS) and photodiode(PD). By using the low noise hybrid pixel structure, dark currents qm be suppressed significantly. The pinned photodiode can also be optimized for quantum efficiency and reduce the noise of dark current. The spectral response of the pinned photodiode on the SOI handle wafer is very flat between 400 nm and 700 nm and the dark current that is higher than desired is about 10 nA/cm2 at a $V_{DD}$ of 2 V.

• Journal of Sensor Science and Technology
• /
• v.30 no.2
• /
• pp.114-118
• /
• 2021

In this study, the sensitivity of an active pixel sensor (APS) was adjusted by employing a gate/body-tied (GBT) p-channel metal-oxide semiconductor field-effect transistor (PMOSFET)-type photodetector with a transfer gate. A GBT PMOSFET-type photodetector can amplify the photocurrent generated by light. Consequently, APSs that incorporate GBT PMOSFET-type photodetectors are more sensitive than those APSs that are based on p-n junctions. In this study, a transfer gate was added to the conventional GBT PMOSFET-type photodetector. Such a photodetector can adjust the sensitivity of the APS by controlling the amount of charge transmitted from the drain to the floating diffusion node according to the voltage of the transfer gate. The results obtained from conducted simulations and measurements corroborate that, the sensitivity of an APS, which incorporates a GBT PMOSFET-type photodetector with a built-in transfer gate, can be adjusted according to the voltage of the transfer gate. Furthermore, the chip was fabricated by employing the standard 0.35 ㎛ complementary metal-oxide semiconductor (CMOS) technology, and the variable sensitivity of the APS was thereby experimentally verified.

• Journal of Sensor Science and Technology
• /
• v.19 no.4
• /
• pp.328-335
• /
• 2010

We have designed and fabricated an active pixel sensor(APS) using an optimized n-well/gate-tied p-channel metal oxide semiconductor field effect transistor(PMOSFET)-type photodetector with a built-in transfer gate. This photodetector has a floating gate connected to n-well and a built-in transfer gate. The photodetector has been optimized by changing the length of the transfer gate. The APS has been fabricated using a 0.35 ${\mu}m$ standard complementary metal oxide semiconductor(CMOS) process. It was confirmed that the proposed APS has a wider dynamic range than the APS using the previously proposed photodetector and a higher sensitivity than the conventional APS using a p-n junction photodiode.

• Journal of the Microelectronics and Packaging Society
• /
• v.27 no.2
• /
• pp.1-10
• /
• 2020

The technology and market size of image sensors continue to develop thanks to the release of image sensors that exceed 100 million pixels in 2019 and expansion of black box camera markets for vehicles in addition to existing mobile applications. We review the technology flow of image sensors that have been constantly evolving for 40 years since Hitachi launched a 200,000-pixel image sensor in 1979. Although CCD has made inroads into image sensor market for a while based on good picture quality, CMOS image sensor (CIS) with active pixels has made inroads into the market as semiconductor technology continues to develop, since the electrons generated by the incident light are converted to the electric signals in the pixel, and the power consumption is low. CIS image sensors with superior characteristics such as high resolution, high sensitivity, low power consumption, low noise and vivid color continue to be released as the new technologies are incorporated. At present, new types of structures such as Backside Illumination and Isolation Cell have been adopted, with better sensitivity and high S/N ratio. In the future, new photoconductive materials are expected to be adopted as a light absorption part in place of the pn junction.

• Journal of Sensor Science and Technology
• /
• v.19 no.4
• /
• pp.285-290
• /
• 2010

In this paper, a dynamic range(DR) extension technique based on a 3-transistor active pixel sensor(APS) and dual image sampling is proposed. The feature of the proposed APS is that the APS uses two or more photodiodes with different sensitivities, such as a high-sensitivity photodiode and a low-sensitivity photodiode. Compared with previously proposed wide DR(WDR) APS, the proposed approach has several advantages, such as no-external equipments or signal processing, no-additional time-requirement for additional charge accumulation, simple operation and adjustable DR extension by controlling parasitic capacitance and sensitivity of two photodiodes. Approximately 16 dB of DR extension was evaluated from the simulation for the situation of 10 times of sensitivity difference and the same size of parasitic capacitance between those two photodiodes.