• 센서학회지
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• 제22권4호
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• pp.256-261
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• 2013

This paper presents an extension of the dynamic range in a complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) using a stacked photodiode and feedback structure. The proposed APS is composed of two additional MOSFETs and stacked P+/N-well/P-sub photodiodes as compared with a conventional APS. Using the proposed technique, the sensor can improve the spectral response and dynamic range. The spectral response is improved using an additional stacked P+/N-well photodiode, and the dynamic range is increased using the feedback structure. Although the size of the pixel is slightly larger than that of a conventional three-transistor APS, control of the dynamic range is much easier than that of the conventional methods using the feedback structure. The simulation and measurement results for the proposed APS demonstrate a wide dynamic range feature. The maximum dynamic range of the proposed sensor is greater than 103 dB. The designed circuit is fabricated by the $0.35-{\mu}m$ 2-poly 4-metal standard CMOS process, and its characteristics are evaluated.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1086-1087
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• 2009

A small temperature sensor is designed in a 0.35um CMOS process. Transistors operating in the intermediate inversion region are employed in the core of the sensor. This temperature sensor operates in $-50^{\circ}C{\sim}120^{\circ}C$ with ${\pm}2^{\circ}C$ of accuracy after two-point calibration. This temperature sensor can be placed in the active pixel area of a display panel to measure the temperature of the display panel for temperature compensation.

• 센서학회지
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• 제21권6호
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• pp.413-419
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• 2012

A dynamic range extension technique is proposed based on a 3-transistor active pixel sensor (APS) with gate/body-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector using a feedback structure. The new APS consists of a pseudo 3-transistor APS and an additional gate/body-tied PMOSFET-type photodetector, and to extend the dynamic range, an NMOSFET switch is proposed. An additional detector and an NMOSFET switch are integrated into the APS to provide negative feedback. The proposed APS and pseudo 3-transistor APS were designed and fabricated using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) process. Afterwards, their optical responses were measured and characterized. Although the proposed pixel size increased in comparison with the pseudo 3-transistor APS, the proposed pixel had a significantly extended dynamic range of 98 dB compared to a pseudo 3-transistor APS, which had a dynamic range of 28 dB. We present a proposed pixel that can be switched between two operating modes depending on the transfer gate voltage. The proposed pixel can be switched between two operating modes depending on the transfer gate voltage: normal mode and WDR mode. We also present an imaging system using the proposed APS.

• 센서학회지
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• 제15권5호
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• pp.341-346
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• 2006

We have fabricated SOI CMOS active pixel image sensor with the pinned photodiode on handle wafer in order to reduce dark currents and improve spectral response. The structure of the active pixel image sensor is 4 transistors APS which consists of a reset and source follower transistor on seed wafer, and is comprised of the photodiode, transfer gate, and floating diffusion on handle wafer. The source of dark current caused by the interface traps located on the surface of a photodiode is able to be eliminated, as we apply the pinned photodiode. The source of dark currents between shallow trench isolation and the depletion region of a photodiode can be also eliminated by the planner process of the hybrid bulk/SOI structure. The photodiode could be optimized for better spectral response because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. The dark current was about 6 pA at 3.3 V of floating diffusion voltage in the case of transfer gate TX = 0 V and TX=3.3 V, respectively. The spectral response of the pinned photodiode was observed flat in the wavelength range from green to red.

• 센서학회지
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• 제17권1호
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• pp.41-52
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• 2008

In this paper, a circuit analysis of the complementary CMOS active pixel and readout circuit is carried out. Complementary pixel structure which is different from conventional 3TR APS structure is consist of photo diode, reset PMOS, several NMOSs and PMOSs sets for complementary signals. Photo diode is modelled with Medici device program. HSPICE was used to analyze the variation of the signal feature depending on light intensity using $0.5{\mu}M$ standard CMOS process. Simulation results show that the output signal range is from 0.8 V to 4.5 V. This signal range increased 135 % output dynamic range compared to conventional 3TR pixel in the condition of 5 V power supply.

• 센서학회지
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• 제21권1호
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• pp.7-12
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• 2012

In this paper, we propose a 4-transistor active pixel sensor(APS) with a novel correlated double sampling(CDS) circuit for the purpose of extending dynamic range. Dual sampling techniques can overcome low-sensitivity and temporal disparity problems at low illumination. To accomplish this, two images are obtained at the same time using different sensitivities. The novel CDS circuit proposed in this paper contains MOS switches that make it possible for the capacitance of a conventional CDS circuit to function as a charge pump, so that the proposed APS exhibits an extended dynamic range as well as reduced noise. The designed circuit was fabricated by using $0.35{\mu}m$ 2-poly 4-metal standard CMOS technology and its characteristics have been evaluated.

• 대한전자공학회논문지SD
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• 제48권2호
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• pp.20-27
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• 2011

모바일 기기에 장착되는 CMOS 이미지 센서(CIS) 칩은 배터리 용량의 한계로 인해 저전력 소모를 요구한다. 본 논문에서는 전력소모를 줄일 수 있는 데이터 플립플롭 회로와 새로운 저전력 구조의 Single-Slope A/D Converter(SS-ADC)를 사용한 이미지 센서를 설계하여 모바일 기기에 사용되는 CIS 칩의 전력 소모를 감소시켰다. 제안하는 CIS는 $2.25um{\times}2.25um$ 면적을 갖는 4-Tr Active Pixel Sensor 구조를 사용하여 QVGA($320{\times}240$)급 해상도를 갖도록 설계되었으며 0.13um CMOS 공정에서 설계되었다. 실험 결과, CIS 칩 내부의 SS-ADC 는 10-b 해상도를 가지며, 동작속도는 16 frame/s 를 만족하였고, 전원 전압 3.3V(아날로그)/1.8V(Digital)에서 25mW의 전력 소모를 보였다. 측정결과로부터 제안된 CIS 칩은 기존 CIS 칩에 비해 대기시간동안 약 22%, 동작시간동안 약 20%의 전력이 감소되었다.

• 센서학회지
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• 제24권2호
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• pp.131-136
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• 2015

This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitor and feedback structure. The designed circuit has been fabricated by using $0.18{\mu}m$ 1-poly 6-metal standard CMOS technology. This sensor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposed pixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity in high light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. The capacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed structure, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results demonstrate wide dynamic range feature of the proposed PPS.

• 센서학회지
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• 제26권2호
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• pp.85-90
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• 2017

A wide dynamic range (WDR) CMOS image sensor (CIS) was developed with a specialized readout architecture for realizing high-sensitivity (HS) and low-sensitivity (LS) reading modes. The proposed pixel is basically a three-transistor (3T) active pixel sensor (APS) structure with an additional transistor. In the developed WDR CIS, only one mode between the HS mode for relatively weak light intensity and the LS mode for the strong light intensity is activated by an external controlling signal, and then the selected signal is read through each column-parallel readout circuit. The LS mode is implemented with the column capacitors and a feedback structure for adjusting column capacitor size. In particular, the feedback circuit makes it possible to change the column node capacitance automatically by using the incident light intensity. As a result, the proposed CIS achieved a wide dynamic range of 94 dB by synthesizing output signals from both modes. The prototype CIS is implemented with $0.18-{\mu}m$ 1-poly 6-metal (1P6M) standard CMOS technology, and the number of effective pixels is 176 (H) ${\times}$ 144 (V).

• 한국콘텐츠학회논문지
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• 제13권10호
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• pp.54-61
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• 2013

본 논문에서는 하드웨어 기반의 영상 신호 윤곽선 검출을 위한 하드웨어기반의 알고리즘으로 CMOS 이미지 센서의 인접픽셀과 아날로그 상관기로 구성되는 윤곽선 검출기를 제안한다. 제안하는 이미지 윤곽 검출기는 각 열(column)마다 비교기를 공유하고, 비교기는 기준전압과 비교를 통해 대상 픽셀의 윤곽선 여부를 판별한다. 이미지 센서와 직접적으로 연결된 윤곽선 검출 회로는 기존의 연구와 비교하여 면적은 4배, 그리고 전력소모는 20 % 감소하는 결과를 보였다. 또한 외부에서 기준전압을 제어할 수 있어, 윤곽선 검출의 민감도를 조절하기에 유용한 장점을 가진다. 0.18 ${\mu}m$ CMOS 공정에서 제작된 칩은 34%의 fill factor를 가지며, 픽셀 당 0.9 ${\mu}W$의 전력소모를 가진다.