• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.61-67
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• 2009

This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.32-42
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• 2007

The substrate resistance is modeled to estimate the performance degradation of analog circuits by substrate noise in a $0.35{\mu}m$ twin-well non-epitaxial CMOS process. The substrate resistance model equations are applied to the P+ guard-ring isolation structure and a good match was achieved between measurements and models. The substrate resistance is divided into four types and a semi-empirical model equation is obtained for each type of substrate resistance. The rms(root-mean-square) error of the substrate resistance model is below 10% compared with the measured resistance. To apply this substrate resistance model to the P+ guard ring structure, ADS(Advanced Design System) circuit simulation results are compared with the measurement results using Network Analyzer, and relatively good agreements are obtained between measurements and simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.847-853
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• 2016

Applications of Si have been increasingly exploited and extended to More-Moore, More-than-Moore, and beyond-CMOS approaches. Ge is regarded as one of the supplements for Si owing to its higher carrier mobilities and peculiar band structure, facilitating both advanced and optical applications. As an emerging metal-oxide device, the junctionless field-effect transistor (JLFET) has drawn considerable attention because of its simple process, less performance fluctuation, and stronger immunity against short-channel effects due to the absence of anisotype junctions. In this study, we investigated lateral field scalability, which is equivalent to channel-length scaling, in Si and Ge JLFETs. Through this, we can determine the usability of Si CMOS and hypothesize its replacement by Ge. For simulations with high accuracy, we performed rigorous modeling for ${\mu}_n$ and ${\mu}_p$ of Ge, which has seldom been reported. Although Ge has much higher ${\mu}_n$ and ${\mu}_p$ than Si, its saturation velocity ($v_{sat}$) is a more determining factor for maximum $I_{on}$. Thus, there is still room for pushing More-Moore technology because Si and Ge have a slight difference in $v_{sat}$. We compared both p- and n-type JLFETs in terms of $I_{on}$, $I_{off}$, $I_{on}/I_{off}$, and swing with the same channel doping and channel length/thickness. $I_{on}/I_{off}$ is inherently low for Ge but is invariant with $V_{DS}$. It is estimated that More-Moore approach can be further driven if Si is mounted on a JLFET until Ge has a strong possibility to replace Si for both p- and n-type devices for ultra-low-power applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.549-557
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• 2012

In this paper an on-chip photo energy harvesting system with MPPT(Maximum Power Point Tracking) control is proposed. The ISC(Integrated Solar Cell) is implemented using p-diff/n-well diodes available in CMOS processes. MPPT control is implemented using the linear relationship between the open-circuit voltage of a PV(Photovoltaic) cell and its MPP(Maximum Power Point) voltage such that a small pilot PV cell can track the MPP of a main PV cell in real time. Simulation results show that the designed circuit with the MPPT control delivers the MPP voltage to load even though the load is heavy such that the load circuit can operate properly. The proposed circuit is designed in 0.18um CMOS process. The designed main PV cell and pilot PV cell occupy $8mm^2$ and $0.4mm^2$ respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.187-191
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• 2007

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.504-512
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• 2010

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

• Journal of Sensor Science and Technology
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• v.5 no.1
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• pp.43-50
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• 1996

This paper presents a manufacture of the multiple subjects biotelemetry system using custom CMOS IC fabricated $1.5{\mu}m$ n-well process technology. The implantable circuits of the system except sensor interface circuits including FM transmitter are fabricated on a single chip with the sire of $4{\times}4mm^{2}$. It is possible to assemble the implantable system in a hybrid package as small as $3{\times}3{\times}2.5cm$ by using this chip, It's main function is to enable continuous measurement simultaneously up to 7-channel physiological signals from the selected one among 8 subjects. Another features of this system are to enable continuous measurement of physiological signals, and to accomplish ON/OFF switching of an implanted battery by subject selection signal with command signal from the external circuit. If this system is coupled with another appropriate sensors in medical field, various physiological parameters such as pressure, pH and temperature are to be measured effectively in the near future.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.613-618
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• 2015

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.963-969
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• 2008

This paper presents 6bit 100MHz Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100MHz Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282mW of power dissipation with 1.8V of Supply Voltage, 100MHz of conversion rate. And 35.027dBc, 31.253dB SFDR and 4.8bits, 4.2bits ENOB with 12.5MHz, 50MHz of each input frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.343-345
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• 2013

This paper describes a phase-locked loop (PLL) that generates a 51-phase clock with the operating frequency of 125MHz. To generate 51-phase clock with a frequency of 125 MHz, the proposed PLL uses three voltage controlled oscillators (VCOs) which are connected by resistors. Each VCO consists of 17 delay-cells. An resistor averaging scheme, which makes three VCOs to connect with each other, makes it possible to generates 51-phase clock of the same phase difference. The proposed PLL is designed by using 65 nm CMOS process with a 1.0 V supply. At the operating frequency of 125 MHz, the simulated DNL and peak-to-peak jitter are +0.0016/-0.0020 LSB and 1.07 ps, respectively. The area and power consumption of the implemented PLL are $290{\times}260{\mu}m^2$ and 2.5 mW, respectively.