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A Substrate Resistance and Guard-ring Modeling for Noise Analysis of Twin-well Non-epitaxial CMOS Substrate  

Kim, Bong-Jin (Analog IC Systems Laboratory, POSTECH)
Jung, Hae-Kang (Analog IC Systems Laboratory, POSTECH)
Lee, Kyoung-Ho (Analog IC Systems Laboratory, POSTECH)
Park, Hong-June (Analog IC Systems Laboratory, POSTECH)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.4, 2007 , pp. 32-42 More about this Journal
Abstract
The substrate resistance is modeled to estimate the performance degradation of analog circuits by substrate noise in a $0.35{\mu}m$ twin-well non-epitaxial CMOS process. The substrate resistance model equations are applied to the P+ guard-ring isolation structure and a good match was achieved between measurements and models. The substrate resistance is divided into four types and a semi-empirical model equation is obtained for each type of substrate resistance. The rms(root-mean-square) error of the substrate resistance model is below 10% compared with the measured resistance. To apply this substrate resistance model to the P+ guard ring structure, ADS(Advanced Design System) circuit simulation results are compared with the measurement results using Network Analyzer, and relatively good agreements are obtained between measurements and simulations.
Keywords
substrate noise analysis; substrate resistance model; guard-ring; isolation;
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