• ETRI Journal
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• v.30 no.1
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• pp.33-46
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• 2008

This paper presents the experimental results of a low-power low-cost RF transceiver for the 915 MHz band IEEE 802.15.4b standard. Low power and low cost are achieved by optimizing the transceiver architecture and circuit design techniques. The proposed transceiver shares the analog baseband section for both receive and transmit modes to reduce the silicon area. The RF transceiver consumes 11.2 mA in receive mode and 22.5 mA in transmit mode under a supply voltage of 1.8 V, in which 5 mA of quadrature voltage controlled oscillator is included. The proposed transceiver is implemented in a 0.18 ${\mu}m$ CMOS process and occupies 10 $mm^2$ of silicon area.

• ETRI Journal
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• v.40 no.2
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• pp.167-179
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• 2018

This paper proposes an IEEE 802.15.4m compliant TV white-space orthogonal frequency-division multiplexing (TVWS)-(OFDM) radio frequency (RF) transceiver that can be adopted in advanced metering infrastructures, universal remote controllers, smart factories, consumer electronics, and other areas. The proposed TVWS-OFDM RF transceiver consists of a receiver, a transmitter, a 25% duty-cycle local oscillator generator, and a delta-sigma fractional-N phase-locked loop. In the TV band from 470 MHz to 698 MHz, the highly linear RF transmitter protects the occupied TV signals, and the high-Q filtering RF receiver is tolerable to in-band interferers as strong as -20 dBm at a 3-MHz offset. The proposed TVWS-OFDM RF transceiver is fabricated using a $0.13-{\mu}m$ CMOS process, and consumes 47 mA in the Tx mode and 35 mA in the Rx mode. The fabricated chip shows a Tx average power of 0 dBm with an error-vector-magnitude of < 3%, and a sensitivity level of -103 dBm with a packet-error-rate of < 3%. Using the implemented TVWS-OFDM modules, a public demonstration of electricity metering was successfully carried out.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.21-29
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• 1998

As silicon geometry shrinks into deep submicron and the operating speed icreases, higher accuracy is required in the analysis of the propagation delays of the gates and interconnects in an ASIC. In this paper, the driving characteristics of a CMOS gate is represented by a gatedriver model, consisting of a linear resistor $R_{dr}$ and an independent ramp voltage source $V_{dr}$ . We drivered $R_{dr}$ and $V_{dr}$ as the functions of the timing data representing gate driving capability and an effective capacitance $C_{eff}$ reflecting resistance shielding effect by interconnet circuits. Through iterative applications of these equations and AWE algorithm, $R_{dr}$ , $V_{dr}$ and $C_{eff}$ are comuted simulataneously. then, the gate delay is decided by $C_{eff}$ and the interconnect circuit delay is determined by $R_{dr}$ and $V_{dr}$ . this process has been implemented as an ASIC timing analysis program written in C language and four real circuits were analyzed. In all cases, we found less than 5% of errors for both of gate andinterconnect circuit delays with a speedup factor ranging from a few tens to a few hundreds, compared to SPICE.SPICE.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.739-742
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• 2005

In this paper, an efficient detection algorithm for the flicker, which is caused by mismatching between light frequency and exposure time at CMOS image sensor (CIS), is proposed. The flicker detection can be implemented by specific hardware or complex signal processing logic. However it is difficult to implement on single chip image sensor, which has pixel, CDS, ADC, and ISP on a die, because of limited die area. Thus for the flicker detection, the simple algorithm and high accuracy should be achieved on single chip image sensor,. To satisfy these purposes, the proposed algorithm organizes only simple operation, which calculates the subtraction of horizontal luminance mean between continuous two frames. This algorithm was verified with MATLAB and Xilinx FPGA, and it is implemented with Magnachip 0.18 standard cell library. As a result, the accuracy is 95% in average on FPGA emulation and the consumed gate count is about 7,500 gates (@40MHz) for implementation using Magnachip 0.18 process.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.877-880
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• 2005

This paper describes a PLL frequency synthesizer for wireless LNA applications. The design is focused mainly on low-power and low-phase noise characteristics. A 128/129 dual-modulus prescaler has been designed using the proposed TSPC D flip-flops for high-speed operation and low-power consumption The designed synthesizer includes all building blocks for elimination of external components, other than the crystal. Its operating frequency can be programmed by external data. The frequency synthesizer has been designed using a $0.25{\mu}m$ CMOS process parameters. It operates in the frequency range of 2GHz to 3GHz and consumes 3.2mA at 2.5GHz from a 2.5V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.192-197
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• 2009

This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.3
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• pp.207-214
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• 2016

Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

• Journal of IKEEE
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• v.15 no.1
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• pp.37-42
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• 2011

In this paper, the high-voltage novel devices have been fabricated by 0.35 um BCD (Bipolar-CMOS-DMOS) process. Electrical characteristics of 20 V level BJT device, 30/60 V HV-CMOS, and 40/60 V LDMOS are analyzed. Also, the vertical/lateral BJT with the high-current gain and LIGBT with the high-voltage are proposed. In the experimental results, vertical/lateral BJT has breakdown voltage of 15 V and current gain of 100. The proposed LIGBT with the high-voltage has breakdown voltage of 195 V, threshold voltage of 1.5 V, and Vce, sat of 1.65 V.

• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.309-314
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• 2014

This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with $0.18-{\mu}m$ CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.