• Transactions on Electrical and Electronic Materials
• /
• v.15 no.3
• /
• pp.139-143
• /
• 2014

In this paper, an integrated low-voltage control circuit is introduced for a charge pump DC-DC boost converter. By exploiting the advantage of the integration of the feedback control circuit within CMOS technology, the charge pump boost converter offers a low-current operation with small ripple voltage. The error amplifier, comparator, and oscillator in the control circuit are designed with the supply voltage of 3.3 V and the operating frequency of 1.6~5.5 MHz. The charge pump converter with the 4 or 8 pump stages is measured in simulation. The test in the $0.35{\mu}m$ CMOS process shows that the load current and ripple ratio are controlled under 1 mA and 2% respectively. The output-voltage is obtained from 4.8 ~ 8.5 V with the supply voltage of 3.3 V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.571-574
• /
• 2008

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.12B
• /
• pp.1695-1702
• /
• 2001

This paper describes a design of CMOS infrared (IR) wireless data link IC which can be used in IrDA(Infrared Data Association) application from 4 Mb/s to 100 Mb/s The implemented chip consists of variable gain transimpedance amplifier which has a gain range from 60 dB to 100 dB, AGC (automatic gain control) circuits, AOC(automatic offset control) loop, 4 PPM (pulse position modulation) modulator/demodulator and DLL(delay locked loops). This infrared optical link If was implemented using commercial 0.25 um 1-poly 5-metal CMOS process. The chip consumes 25 mW at 100 Mb/s with 2.5 V supply voltage excluding buffer amplifier. The die area of prototype IC is 1.5 mm $\times$ 1 mm.

• Journal of Sensor Science and Technology
• /
• v.23 no.2
• /
• pp.87-93
• /
• 2014

In this paper, we propose a block-based low-power complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a simple pixel structure for power efficiency. This method, which uses an additional computation circuit, makes it possible to reduce the power consumption of the pixel array. In addition, the computation circuit for a block-based CIS is very flexible for various types of pixel structures. The proposed CIS was designed and fabricated using a standard CMOS 0.18 ${\mu}m$ process, and the performance of the fabricated chip was evaluated. From a resultant image, the proposed block-based CIS can calculate a differing contrast in the block and control the operating voltage of the unit blocks. Finally, we confirmed that the power consumption in the proposed CIS with a simple pixel structure can be reduced.

• Journal of Sensor Science and Technology
• /
• v.26 no.4
• /
• pp.223-227
• /
• 2017

Conventional CMOS image sensors (CISs) have a trade-off relationship between dynamic range and sensitivity. In addition, their sensitivity is determined by the photodiode capacitance. In this paper, CISs that consist of dual-sensitivity photodiodes in a unit pixel are proposed for achieving wide dynamic ranges. In the proposed CIS, signal charges are generated in the dual photodiodes during integration, and these generated signal charges are accumulated in the floating-diffusion node. The signal charges generated in the high-sensitivity photodiodes are transferred to the input of the comparator through an additional source follower, and the signal voltages converted by the source follower are compared with a reference voltage in the comparator. The output voltage of the comparator determines which photodiode is selected. Therefore, the proposed CIS composed of dual-sensitivity photodiodes extends the dynamic range according to the intensity of light. A $94{\times}150$ pixel array image sensor was designed using a conventional $0.18{\mu}m$ CMOS process and its performance was simulated.

• Journal of Information Display
• /
• v.3 no.2
• /
• pp.1-5
• /
• 2002

A CMOS driving circuit for active matrix type polymer electroluminescent displays was designed to develop an on-chip microdisplay on the single crystal silicon wafer substrate. The driving circuit is a conventional structure that is composed of the row, column and pixel driving parts. 256 gray scales were implemented using pulse amplitude modulation method. The 2-transistor driving scheme was adopted for the pixel driving part. The layout was carried out considering the compatibility with the standard CMOS process. Judging from the layout of the driving circuit, it turns that it is possible to implement a high-resolution display about 400 ppi resolution. Through the HSPICE simulation, it was verified that this circuit is capable of driving a VGA signal mode display and implementing 256 gray levels.

• Proceedings of the KIEE Conference
• /
• 2002.07d
• /
• pp.2577-2579
• /
• 2002

In this paper, we describe a CMOS DC-DC converter with a variable output voltage(8-12V @100mA) for a portable battery-operated system applications. The proposed DC-DC converter is used along with a Pulse-Frequency Modulation (PFM) method and consists of a reference circuit, a feedback resistor, a controller, and an internal oscillator. The integrated DC-DC converter with two external passive components(L.C) has been designed and fabricated on a 0.6${\mu}m$ 2-poly, 3-metal CMOS process and could be applied to the Personal Digital Assistants(PDA), Cellular Phone, Laptop Computer, etc.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.2 no.1
• /
• pp.30-40
• /
• 2002

A 2.45GHz double-balanced modified Gilbert-type CMOS up-conversion mixer design is introduced, where the PMOS current-reuse bleeding technique is demonstrated to be efficient in improving conversion gain, linearity, and noise performance. An LO buffer is included in the mixer design to perform single-ended to differential conversion of the LO signal on chip. Simulation results of the design based on careful modeling of all active and passive components are examined to explain in detail about the characteristic improvement and degradation provided by the proposed design. Two kinds of chips were fabricated using a standard $0.35\mu\textrm$ CMOS process, one of which is the mixer chip without the LO buffer and the other is the one with it. The measured characteristics of the fabricated chips are quite excellent in terms of conversion gain, linearity, and noise, and they are in close match to the simulation results, which demonstrates the adequacy of the modeling approach based on the macro models for all the active and passive devices used in the design. Above all the benefits provided by the current-reuse bleeding technique, the improvement in noise performance seems most valuable.

• Proceedings of the IEEK Conference
• /
• 2002.07c
• /
• pp.1543-1546
• /
• 2002

The expandable 4 bit adder/subtracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$ CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.505-506
• /
• 2006

In this paper, the linearization technique for CMOS low-noise amplifier (LNA) using the derivative superposition method through the multiple gated transistors configuration is presented. LNA based on 0.13um RF CMOS process has been implemented with a modified cascode configuration using multiple gated common source transistors to fulfill a high linearity. Compared with a conventional cascode type LNA, the third order input intercept point (IIP3) per DC power consumption (IIP3/DC) is improved by 3.85 dB. The LNA achieved 2.5-dBm IIP3 with 13.4-dB gain, 3.6 dB NF at 2.4 GHz consuming 8.56 mA from a 1.5-V supply.