• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.189-196
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• 2015

In this paper, we present a rotating auto-zeroing offset cancellation technique, which can improve the performance of touch screen sensing circuits. Our target touch screen detection method employs multiple continuous sine waves to achieve a high speed for large touch screens. While conventional auto-zeroing schemes cannot handle such continuous signals properly, the proposed scheme does not suffer from switching noise and provides effective offset cancellation for continuous signals. Experimental results show that the proposed technique improves the signal-to-noise ratio by 14 dB compared to a conventional offset cancellation scheme. For the realistic simulation results, we used Cadence SPECTRE with an accurate TSP model and noise source. We also applied an asymmetric device size (10% MOS size mismatch) to the OP Amp design in order to measure the effectiveness of offset cancellation. We implemented the proposed circuit as part of a touch screen controller system-on-chip by using a Magnachip/SK Hynix 0.18-µm complementary metal-oxide semiconductor (CMOS) process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3246-3255
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• 1996

A threshold voltage extraction scheme which does not need matched replica of the MOSFET under test is proposed. In contrast to alternative methods, the accuracy of the proposed scheme does not depend on the matching of the test transistors. The proposed scheme has been implemented in a matching-free way using a switched-capacitor subtracting ampliier and a dynmic current mirror. Nonideal effects associated with these circuits, such as non-zero offset voltages and finite gains of op-amps, capcitor mismateches, and charge injection of MOS switches, are investigated and compensated. The circuit has been designed using ISRC 1.5.mu.m CMOS process parameters andfabricated at Inter-University semiconductor Research Center, and its performance has been evaluated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.7
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• pp.667-674
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• 2005

In this paper the gate overlap length of the LDMOST is optimized for obtaining longer device lifetime. The LDMOSI device with drift region is fabricated using the $0.25\;{\mu}m$ CMOS Process. The gate overlap lengths on drift region are $0.1\;{\mu}m,\;0.4\;{\mu}m\;0.8\;{\mu}m\;and\;1.1\;{\mu}m$, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with gate overlap length of $0.4\;{\mu}m$ showed the longest on-resistance lifetime, 0.02 years and breakdown voltage of 22 V and on-resistance of $23\;m\Omega{\cdot}mm^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.26-31
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• 2002

To realize a high integrated Flash memory utilizing SONOS memory devices, the NOR type 1TC(one Transistor Cell) SONOS Flash arrays are fabricated and characterized. This SONOS Flash arrays with common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cell is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$. To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and Bit line erase method are selected as the write operation and the erase method, respectively. The disturbance characteristics according to the write/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• Electrical & Electronic Materials
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• v.7 no.2
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• pp.157-164
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• 1994

DRAM(Dynamic Random Access Memory)은 반도체 소자중 가장 대표적인 기억소자로, switch역활을 하는 1개의 transistor와 data의 전하를 축적하는 1개의 capacitor로 구성된 단순한 구조와 고집적화에 용이하다는 이점을 바탕으로, supercomputer에서 가전제품 및 산업기기에 이르기 까지 널리 이용되어왔다. 한편으로 DRAM사업은 고가의 장치사업으로 조기시장 진입을 위하여 초기에 막대한 자본투자, 급속한 기술발전, 짧은 life cycle, 가격급락등이 심하여, 시한내 투자회수가 이루어져야 하는 위험도가 큰 기회사업이라는 양면성도 가지고 있다. 이러한 관점때문에 새로운 DRAM기술은 매 세대마다 끊임없이 빠른 속도로 개발되어왔다. 그러나 sub-micron이하의 DRAM세대로 갈수록 그에 대한 신기술은 점차 어렵게 되어가고, 한편으로는 system의 다양화에 따른 요구도 강하여, 이제는 통상적인 DRAM의 고집적화/저가의 전략만으로는 생존하기 어려운 실정이므로 개발전략도 수정하여야만 할 것이다. 이러한 어려운 기술한계를 극복하기 위하여 새로운 소자기술 및 공정개발에 대한 breakthrough가 이루어져야 할 것이다. 이러한 관점에서 현재까지의 DRAM개발 추이와 향후의 기술방향에 관하여 몇가지 중요한 item을 설정하여 논의해 보기로 한다.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2786-2788
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• 1999

In this paper, a mixed mode exciting resonant inverter topology applicable to high performance electronic ballast is presented. Mixed mode exciting technique combines the attractive features of self exciting resonant inverter with those of external exciting one. The control IC is designed and manufactured by using a 0.8um CMOS process for 5V operation and has only 8 pins. This performs the operations of filament preheating, dimming control, output power regulation and protections. The mixed mode exciting resonant inverter with control IC has very simple structure, high performance and expensive manufacturing cost.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.5
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• pp.424-428
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• 2010

This paper describes the design and analysis of AlN piezoelectric micro energy harvester. The harvester was designed to convert ambient vibration energy to electrical power as a AlN piezoelectric material compatible with CMOS (complementary metal oxide semiconductor) process. To cut off the leakage current, AlN was used as the insulating layer. Also, Mo was used for the excellent c-axis crystal growth as the bottom electrode. The AlN harvester which it has the low operating frequency was designed by using the ANSYS FEA (finite element analysis). From the simulation results, the resonance frequency of designed model is about 360 Hz and analyzed the bending mode, displacement and expectation output.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.188-191
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• 1993

Silicon flow sensor which can detect the magnitude and direction of two dimensional air flow was designed and fabricated by CMOS process and bulk micromachining technique. The flow sensor consists of three-layered dielectric diaphragm a heater at the center of the diaphragm and four thermopiles surrounding the heater at each side of diaphragm as sensing elements. This diaphragm structure contributes to improve the sensitivity due to excellent thermal isolation property of dielectric materials and its tiny thickness. The flow sensor has good axial symmetry to sense 2-D air flow with the optimized sensing position in the given structure. Measured sensitivity of our sensor is $18.7mV/(m/s)^{1/2}$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.5
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• pp.1005-1009
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• 2010

This paper presents a digitally-controlled filter calibration technique for biquad RC filter using self oscillation. The biquad RC filter is converted to a fully-differential ring oscillator by changing its resistor connections, where the oscillation frequency reflects the cut-off frequency. The proposed calibration circuit measures the oscillation frequency by counting with a fixed higher-frequency clock and then tunes it to a desired frequency with a digital frequency-locked loop including a PI controller. Because the proposed circuit directly measures the cut-off frequency of the filter itself and calibrates it with the small area digital circuits, the area and the power consumption are much small compared with conventional works. When it is implemented in a 65nm CMOS process, the calibration circuit except the filter consumes the area of 80um X 50um and power consumption is 443uA at 1.2 V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.143-146
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• 2016

A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just $0.01mm^2$. The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.