• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.11
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1553-1558
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• 2007

This paper presents a vision based autonomous inspection system for welding quality control of car sinking seat. In order to overcome the precision error that arises from a visible inspection by operator in the manufacturing process of a car sinking seat, this paper proposes the MVWQC (machine vision based welding quality control) system. This system consists of the CMOS camera and NI machine vision system. The image processing software for the system has been developed using the NI vision builder system. The geometry of welding bead, which is the welding quality criteria, is measured by using the captured image with median filter applied on it. Experiments have been performed to verify the proposed MVWQC of car sinking seat.

• Journal of information and communication convergence engineering
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• v.7 no.1
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• pp.66-71
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• 2009

A novel sensing scheme using resistive characteristics of the finger is proposed. ESD problem is more harmful than a capacitive fingerprint sensor in a resistive fingerprint sensor, because the sensor plate is directly connected to the sensing cell. The proposed circuit is more robust than conventional circuit for ESD. The sensor plate and sensing cell are isolated by capacitor. The pixel level simple detection circuit is fully digital operation unlike that of the capacitive sensing cell. The sensor circuit blocks are designed and simulated in a standard CMOS $0.35{\mu}m$ process. The proposed circuit is more stable and effective than a typical circuit.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.275-278
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• 2008

In this paper, I propose the full CMOS FLL(frequency locked loop) circuit. The proposed FLL circuit has a simple structure which contains a FVC(frequency-to-voltage converter), an operational amplifier and a VCO(voltage controlled oscillator). The operation of FLL circuit is based on frequency comparison by the two FVC circuit blocks. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. The circuit is designed by 0.35${\mu}m$ process and simulation carried out with HSPICE. Simulation results are shown to illustrate the performance of the proposed FLL circuit.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.193-198
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• 2005

NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.216-218
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• 2005

Planar spiral inductors on silicon substrates were optimally designed using MATLAB, which is a tool to perform numerical computations with matrices. The equivalent circuit parameters of the spiral inductors were extracted from the data measured from the spiral inductors fabricated using a 0.18 $\mu\textrm{m}$ RF CMOS process. The metal width, which is a critical design parameter, was optimized for the maximum quality factor with respect to the operating frequency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.523-526
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• 2001

In this paper, we design and fabricate the high-efficiency and low-power switched-capacitor DC-DC converter. This converter consists of internal oscillator, output driver and output switches. The internal oscillator has 100kHz oscillation frequency and the output switches composed of one pMOS transistor and three nMOS transistors. According to the configuration of two external capacitors, the converter has three functions that are the Inverter, Doubler and Divider. The proposed converter is fabricated through the 0.8$\mu\textrm{m}$ 2-poly, 2-metal CMOS process. The simulation and experimental result for fabricated IC show that the proposed converter has the voltage conversion efficiency of 98% and power efficiency more than 95%.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.482-484
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• 2006

This paper describes fast-hopping frequency synthesizers for multi-band OFDM(MB-OFDM) ultra-wide band(UWB) systems. Three different structures in generating 3 center frequencies(3432MHz, 3960MHz, 4488MHz) are designed and compared. The first structure generates 3 center frequencies using only one PLL operating at 4224MHz. The second uses three PLLs operating at corresponding center frequencies. The third employes two PLLs operating at 3960MHz and 528MHz. Simulation results using a 0.18um RF CMOS process parameters show that the third structure exhibit the best characteristics. The band switching time of the proposed synthesizer is less than 1.3ns and the spur is less than -36dBc. The synthesizer consumes 22mA from a 1.8V supply.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.144-147
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• 2005

This paper is proposed an 8$\times$8 bit parallel multiplier for low power consumption. The 8$\times$8 bit parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing tile previous works, this circuit is reduced the power consumption rate of 8.2% and the power-delay-product of 11.1%. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35$\{\mu}m$ standard CMOS process.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.12
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• pp.1870-1877
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• 1990

The electromagnetic properties of P- and n-channel split drain magnetic sensitive MOSFET fabricated using 2\ulcorner design rules and CMOS process technology has been investigated. The achieved output voltage in the double drain MOSFET was 160mV at 10\ulcorner drain current and magnetic flux density of 10kG, and the sensitivity was 1.6x10**3 V/A\ulcornerG. A further higher sensitivity was obtained by introducing a third drain in the split region. In this case, the triple drain MOSFET showed a much higher sensitivity of 2x10**3 V/A\ulcornerG under the same condition. Also, the linearity of output voltage vs. magnetic flux density was excellent.