• Journal of Sensor Science and Technology
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• v.27 no.2
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• pp.93-98
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• 2018

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.98-106
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• 2009

This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.

• Journal of IKEEE
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• v.22 no.4
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• pp.1006-1011
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• 2018

This paper proposes a three level buck converter utilizing multi-bit flying capacitor voltage control. The conventional three-level buck converter can not control the flying capacitor voltage, so that the operation is unstable or the circuit for controlling the flying capacitor voltage can not be applied to the PWM mode. Also when the load current is increased, an error occurs in the inductor voltage. The proposed structure can control the flying capacitor voltage in PWM mode by using differential difference amplifier and common mode feedback circuit. In addition, this paper proposes a 3bit flying capacitor voltage control circuit to optimize the operation of the three level buck converter depending on the load current, and a triangular wave generation circuit using the schmitt trigger circuit. The proposed 3-level buck converter is designed in $0.18{\mu}m$ CMOS process and has an input voltage range of 2.7V~3.6V and an output voltage range of 0.7V~2.4V. The operating frequency is 2MHz, the load current range is 30mA to 500mA, and the output voltage ripple is measured up to 32.5mV. The measurement results show a maximum power conversion efficiency of 85% at a load current of 130 mA.

• Journal of IKEEE
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• v.23 no.3
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• pp.917-924
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• 2019

This paper presents a wideband low noise amplifier (LNA) that is suitable for LTE-Advanced and 5G communication standards employing carrier aggregation (CA). The proposed LNA encompasses a common input stage and a dual output second stage with a buffer at each distinct output. This architecture is targeted to operate in both intra-band (contiguous and non-contiguous) and inter-band CA. In the proposed design, the input and second stages employ a gm enhancement with resistive feedback technique to achieve self-biasing, enhanced gain, wide bandwidth as well as reduced noise figure of the proposed LNA. An up/down power controller controls the single input single out (SISO) and single input multiple outputs (SIMO) modes of operation for inter-band and intra-band operations. The proposed LNA is designed with a 45nm CMOS technology. For SISO mode of operation, the LNA operates from 0.52GHz to 4.29GHz with a maximum power gain of 17.77dB, 2.88dB minimum noise figure and input (output) matching performance better than -10dB. For SIMO mode of operation, the proposed LNA operates from 0.52GHz to 4.44GHz with a maximum voltage gain of 18.30dB, a minimum noise figure of 2.82dB with equally good matching performance. An $IIP_3$ value of -6.7dBm is achieved in both SISO and SIMO operations. with a maximum current of 42mA consumed (LNA+buffer in SIMO operation) from a 1.2V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.4
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• pp.475-483
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• 2012

This paper presents new type of the hybrid supply modulator for the next reconfigurable transmitters. The efficiency of the hybrid supply modulator is one of the most important performance. For enhancement the efficiency, multi-switching structure in the hybrid supply modulator is employed. Additionally, input envelope signal sensing stage is employed for implementation multi-mode operation. To compare the performance of the proposed hybrid supply modulator, the conventional hybrid supply modulator is also designed. The measured efficiency of the proposed hybrid supply modulator is 85 %/84 %/79 % for EDGE/WCDMA/LTE signals which have 384 kHz/3.84 MHz/5 MHz bandwidth, respectively. The efficiency of the proposed hybrid supply modulator is higher than the conventional hybrid supply modulator. Therefore, this structure shows good candidate for the reconfigurable transmitters.