• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.7
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• pp.1282-1287
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• 2007

We investigated the damage of the CMOS IC which manufactured three different technologies by high power microwave. The tests separated the two methods in accordance with the types of the CMOS IC located inner waveguide. The only CMOS IC which was located inner waveguide was occurred breakdown below the max electric field (23.94kV/m) without destruction but the CMOS IC which was connected IC to line organically was located inner waveguide and it was occurred breakdown and destruction below the max electric field. Also destructed CMOS IC was removed their surface and a chip condition was analyzed by SEM. The SEM analysis of the damaged devices showed onchuipwire and bondwire destruction like melting due to thermal effect. The tested results are applied to the fundamental data which interprets the combination mechanism of the semiconductors from artificial electromagnetic wave environment and are applied to the data which understand electromagnetic wave effects of electronic equipments.

• Electronics and Telecommunications Trends
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• v.10 no.1 s.35
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• pp.1-17
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• 1995

본 연구에서는 아날로그 CMOS IC 제조를 위한 CMOS 소자기술 및 수동소자 기술인, 다결정실리콘 저항과 다결정실리콘(I)/산화막/다결정실리콘(II) 구조를 가진 커패시터의 공정기술을 개발하였다. 아날로그 CMOS 공정기술은 디지털 CMOS 공정에서 다결정실리콘 저항과 커패시터 공정이 추가됨으로씨 발생할 수 있는 CMOS 소자특성의 변화를 최소화하는 데 중점을 두어 개발하였다. 최종적으로 개발된 $1.2\mum$ 아날로그 CMOS 공정을 이용하여 10 비트 ADC 및 DACIC를 제작한 후 정상적인 동작을 확인함으로써, $1.2\mum$ 아날로그 CMOS 공정에 의한 아날로그 IC 제작의 응용 가능성을 검증하였다. 개발된 $1.2\mum$ 아날로그 CMOS 공정은 향후 $0.8\mum$ 아날로그 CMOS IC 개발에 크게 기여할 것으로 기대된다.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2005.05a
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• pp.914-921
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• 2005

신제품으로 개발 중인 초소형 CMOS RF 전압 제어발진기(VCO) IC 에 대한 공인된 시험 규격은 현재 개발되어 있지 않다. 또한 제조업체들은 고유의 시험방법을 보유하고 있을 것이나 공개하지 않고 있는 실정이다. 한편 일부 해외 제조업체에서 국제 규격인 IEC 또는 JEDEC 을 기준으로 시험방법을 제시하고 있지만, 이러한 시험규격들은 개별 부품을 솔더링하는 하이브리드 공정을 이용하여 제작된 VCO 를 대상으로 한 것이다. 그러므로 CMOS 반도체 공정을 이용한 IC 형으로 개발 중인 VCO 를 평가하기에는 적합하지 않다. 이에 본 연구에서는 신개발 부품인 CMOS RF VCO IC 에 대한 신뢰성 시험 및 평가 기준을 수립하고, 신뢰성 확보를 위한 신제품 개발 단계에서의 신뢰성 평가 프로세스를 개발하고자 한다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1141-1144
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• 1998

A new design methodology for the shortchannel CMOS IC-package is presented. It is developed by representing the package inductance with an effective lumpedinductance. The worst case maximum-simultaneous-switching noise (SSN) and gate propagation delay due to the package are modeled in terms of driver geometry, the maximum number of simultaneous switching drivers, and the effective inductance. The SSN variations according to load capacitances are investigated with this model. The package design techniques based on the proposed guidelines are verified by performing HSPICE simulations with the $0.35\mu\textrm{m}$ CMOS model parameters.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1141-1144
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• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.

• Korean Journal of Optics and Photonics
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• v.8 no.6
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• pp.500-505
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• 1997

Experimental amorphous photodiode is fabricated on CMOS IC using a-Si:H p-i-n structure. Amorphous photodiode is scuccessfully integrated on CMOS IC using amorphous Si produced by PECVD system. The PECVD system can deposit a-Si:H at low temperature so that photodiode can be integrated with CMOS IC structure without any process incompatibility. The fabricated amorphous photodiode has a breakdown voltage of below -20 V, a leakage current of about 1 $\mu\textrm{A}$, and turn-on voltage of 0.6~0.8 V. It is demonstrated that the photocurrent of optical signal can be turned on and off by a small voltage and the fabricated amorphous p-i-n photodiode can be used as an optical switch.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.555-559
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• 2003

In this paper, a new CMOS RF model for RF IC design including the capacitance effect, the skin effect, and the proximity effect between metal lines on the Si surface is proposed for tile first time for accurately predicting the RF behavior of CMOS devices. The capacitances between metal lines on the Si surface are modeled with the layout. And the skin effect is modeled with a parallel branch added in equivalent circuit of metal line. The proximity effect is modeled by adding the mutual inductance between cross-coupled inductances in the ladder circuit representation. Compared to the BSIM 3v3. the proposed RF model shows good agreements with the measured data and shows well the frequency dependent behavior of devices in GHz ranges.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.393-396
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• 1999

A circuit model of silicon substrate coupling for CMOS RF-IC design is developed. Its characteristics are analyzed by using a simple RC mesh model in order to investigate substrate coupling. The coupling effects due to the substrate were characterized with substrate resistivity, oxide thickness, substrate thickness. and physical distance. Thereby the silicon substrate effects are analytically investigated and verified with simulation. The analysis and simulation of the model have excellent agreements with MEDICI(2D device simulator) simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.57-57
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• 2001

본 논문에서는 RFID를 위한 읽기 전용 CMOS 트랜스폰더를 one-chip으로 설계하였다. 리더에서 공급되는 자기장으로부터 트랜스폰더 칩의 전원을 공급하기 위한 전파정류기를 NMOS 트랜지스터를 사용하여 설계하였으며, 데이터 저장 소자로는 64비트의 ROM을 사용하였다. 메모리에 저장되어 있는 ID 코드는 Manchester 코딩되어 front-end 임피던스 변조 방식으로 리더에 전송된다. 임피던스 변조를 위한 감폭회로로는 리더와 트랜스폰더 사이의 거리가 변해도 일정한 감폭율을 갖는 새로운 감폭회로를 사용하였다. 설계된 회로는 0.65㎛ 2-poly, 2-metal CMOS 공정을 사용하여 IC로 제작되었다. 칩 면적은 0.9㎜×0.4㎜이다. 측정 결과 설계된 트랜스폰더 IC는 인식거리 내에서 약 20∼25%의 일정한 감폭율을 보이며, 125㎑의 RF에 대해 3.9kbps의 데이터 전송속도를 보인다. 트랜스폰더 칩의 전력소모는 읽기 모드시 약 100㎼이다. 인식거리는 약 7㎝이다.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.937-940
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• 2000

This paper describes expandable 4 bit ALU IC using adiabatic and dynamic CMOS circuit technique. It was designed so that the integrated circuit may have the function which is equivalent to HC181 which is CMOS standard logic IC for the comparison, and it was fabricated using a standard 1.2${\mu}$ CMOS process. As the result, the IC has shown that it operates perfectly on all function modes. The power dissipation is 2 order lower than that of HC 181.