• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.42-47
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• 2017

This paper proposes a new series-coupled voltage-controlled oscillator (VCO). The proposed VCO consists of four current-reuse Armstrong VCOs (CRA-VCOs) coupled by four transformers. The series-coupling, current-reuse, and Armstrong topologies improve the phase noise performance by increasing the negative-Gm of the VCO core with half the current consumption of a conventional differential VCO. The proposed VCO consumes 6.54 mW at 9.78 GHz from a 1-V supply voltage. The measured phase noise is -115.1 dBc/Hz at an offset frequency of 1 MHz, and the FoM is -186.5 dBc/Hz. The frequency tuning range is from 9.38-10.52 GHz. The core area is $0.49mm^2$ in a $0.13-{\mu}m$ CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.94-100
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• 2014

In this paper, a design of low power Current-Reuse Voltage Controlled Oscillator (VCO) which has wide tuning range about 1.95 GHz ~ 3.15 GHz is presented. Class-C type is applied to improve phase noise and 2-Step Auto Amplitude Calibration (AAC) is used for minimizing the imbalance of differential VCO output voltage which is main issue of Current-Reuse VCO. The mismatch of differential VCO output voltage is presented about 1.5mV ~ 4.5mV. This mismatch is within 0.6 % compared with VCO output voltage. Proposed Current-Reuse VCO is designed using CMOS $0.13{\mu}m$ process. Supply voltage is 1.2 V and current consumption is 2.6 mA at center frequency. The phase noise is -116.267 dBc/Hz at 2.3GHz VCO frequency at 1MHz offset. The layout size is $720{\times}580{\mu}m^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.83-89
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• 2014

A ku-band complementary cross-coupled differential voltage controlled oscillator is designed, measured and fabricated using $0.18-{\mu}m$ CMOS technology. A 2.4GHz of very wide frequency tuning at oscillating frequency of 14.5GHz is achieved with presented circuit topology and MOS varactors. Measurement results show -1.66dBm output power with 18mA DC current drive from 3.3V power supply. When 5V is applied, the output power is increased to 0.84dBm with 47mA DC current. -74.5dBc/Hz phase noise at 100kHz offset is measured. The die area is $1.02mm{\times}0.66mm$.

• Journal of electromagnetic engineering and science
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• v.10 no.1
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• pp.35-38
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• 2010

A fully integrated parallel-coupled 6-GHz quadrature voltage-controlled oscillator (QVCO) has been designed. The symmetrical parallel-coupled quadrature VCO is implemented using 0.13-${\mu}m$ CMOS process. The measured phase noise is -101.05 dBc/Hz at an offset frequency of 1 MHz. The tuning range of 710 MHz is achieved with a control voltage ranging from 0.3 to 1.4 V. The average output phase error is about $1.26^{\circ}$ including cables and connectors. The QVCO dissipates 10 mA including buffer from the 1.5 V supply voltage. The output characteristic of the differential injection-locked frequency divider (DILFD), which has similar topology to the QVCO, is presented.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.5
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• pp.889-895
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• 2008

In this paper a Fractional-N frequency synthesizer is designed for UHF RFID readers. It satisfies the ISO/IEC frequency band($860{\sim}960MHz$) and is also applicable to mobile RFID readers. A VCO is designed to operate at 1.8GHz band such that the LO pulling effect is minimized. The 900MHz differential I/Q LO signals are obtained by dividing the differential signal from an integrated 1.8GHz VCO. It is designed using a $0.18{\mu}m$ RF CMOS process. The measured results show that the designed circuit has a phase noise of -103dBc/Hz at 100KHz offset and consumes 9mA from a 1.8V supply. The channel switching time of $10{\mu}s$ over 5MHz transition have been achieved, and the chip size including PADs is $1.8{\times}0.99mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1184-1189
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• 2004

A new schematic of quadrature voltage controlled oscillator(QVCO) is designed and fabricated. To obtain quadrature characteristic and low phase noise simultaneously, two differential VCOs are forced to un in quadrature mode by using coupling amplifier with a source degeneration resistor, which is optimized to obtain quadrature accuracy with minimum phase noise degradation. The designed QVCO was fabricated in standard CMOS technology. The measured performance showed the phase noise of below -120 dBc/Hz at 1 MHEz frequency offset, tuning bandwidth of 210 MHz from 2.34 GHz to 2.55 GHz with a tuning voltage varying form 0 to 1.8 V Quadrature error of 0.5 degree and amplitude error of 0.2 dB was measured with conjunction with low-lF mixer. The fabricated QVCO requires 19 mA including 5 mA in the VCO core part fiom a 1.8 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.470-475
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• 2015

This paper presents a wideband Current-Reused Voltage Controlled Oscillator (VCO) with 2-Step Automatic Amplitude Calibration (AAC). Tuning range of the proposed VCO is from 1.95 GHz to 3.15 GHz. The mismatch of differential voltage is within 0.6 %. At 2.423 GHz, the phase noise is -116.3 dBc/Hz at the 1 MHz offset frequency with the current consumption of 2.6 mA. The VCO is implemented $0.13{\mu}m$ CMOS technology. The layout size is $720{\times}580{\mu}m^2$.

• Journal of IKEEE
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• v.26 no.4
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• pp.714-721
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• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.340-343
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• 1999

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.