• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.6B
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• pp.848-855
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• 2001

본 논문에서는 GHz 대역의 고속 클럭 신호를 필요로 하는 데이터 통신 시스템 분야에 응용될 수 있는 새로운 구조의 클럭 및 데이터 복원회로를 제안하였다. 제안된 회로는 고속의 데이터 전송시 주로 사용되는 NRZ 형태의 데이터 복원에 적합한 구조로서 NRZ 데이터가 주입될 경우에 위상동기 회로에 발생하는 주요 잡음원인인 high frequency jitter를 방지하기 위한 새로운 위상 검출구조를 갖추고 있어서 보다 안정적인 클럭을 제공할 수 있다. 또 가변적인 지연시간을 갖는 delay cell을 이용한 위상검출기를 제안하여 위상 검출기가 갖는 dead zone 문제를 없애고, 항상 최적의 동작을 수행하여 빠른 동기 시간을 갖도록 하였다. Gbps급 대용량의 데이터를 복원하기 위한 클럭 생성을 목표로 하여 CMOS 0.25$\mu\textrm{m}$ 공정을 사용하여 설계한 후 그 동작을 HSPICE post-layout simulation을 통해 검증하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.105-111
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• 2013

We have developed an analog associative memory implemented with an analog array which has linear writing and erasing characteristics. The associative memory adopts a winner-take-all strategy. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density. A multiple memory cell configuration is also presented for achieving higher integration density, quick readout, and fast writing. The system technology presented here is ideal for a real time recognition system. We simulate the function of the mechanism by menas of Hspice with $1.2{\mu}$ double poly CMOS parameters of MOSIS fabrication process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.97-103
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• 2002

In this paper, a Logarithmic Video Amplifier(LVA) for radar system or satellite communications is described. The proposed LVA is composed of a input stage, amplification stage, and output stage. As well as a novel series-parallel architecture is proposed for the purpose of wide dynamic range and high speed operation, a newly developed input stage is designed in order to control the voltage level between LVA and detector diode. The LVA is fabricated with a 1.5um 2-poly 2-metal n-well Bi-CMOS technology, and the chip area is 1310 um x 1540 um. From the experimental results, it consumes 190 mW at 10V power supply, the chip has 60 dB dynamic range and 100ns falling time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.32-38
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• 2011

This paper describes implementation of the 5.0GHz RF frequency synthesizer with 0.18${\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get excellent performance of high speed and wide tuning range, N-P MOS core structure and 12 step cap banks have been used in design of the VCO. The chip area including pads for testing is $1.1{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.0{\times}0.4mm^2$. Through analysing of the fabricated frequency synthesizer, we can see that it has wide operation range and excellent frequency characteristics.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.38-49
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• 2001

This paper presents a new voltage down converter(VDC) using charge and discharge current adjustment circuitry that provides high frequency application. This VDC consist of a common driving circuit and compensation circuits: 2 sensors and each driving transistors for controlling gate current of driving transistor. These sensors are operated as adaptive biasing method with high speed and low power consumption. This circuit is designed with a $0.62{\mu}m$ N well CMOS technology. In H-spice simulation results, internal voltage is bounded ( IV, +0.6V) in proposed circuitry when load current rapidly increases and decreases during Gns between 0 and $200m{\Lambda}$. And the recovery time of internal voltage is about 7ns and 10ns when load current increases and decreases respectively. That is fast better than common driving circuit. Total power consumption is about 1.2mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.49-54
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• 2009

This paper describes implementation of the 1.9GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma }-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.2{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.1{\times}0.4mm^2$. The test results show that there is no special spurs except -63.06dB of the 6MHz reference spurs in the PLL circuitry. There is good phase noise performance like -116.17dBc/Hz in 1MHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.6
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• pp.87-93
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• 2008

This paper describes implementation of the 5.0GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.1*0.7mm^2$, and the chip area only core for IP in SoC is $1.0*0.4mm^2$. Through comparing and analysing of the designed two kind of the frequency synthesizer, we can conclude that if we improve a litter characteristics there is no problem to use their as IPs.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.7
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• pp.659-664
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• 2016

In this paper, we suggest operational trans-conductance amplifier(OTA) for current-mode FIR filter that can be used in a digital circuit system requiring high operating frequency and low power consumption. The current-mode signal processing is one of the very innovative design method for a low power consumption system with high operating frequency because it shows a constant power regardless of frequency. From the simulation result using 0.35um CMOS process, when Vdd is 2V, it is confirmed that the proposed circuit showed the dynamic range of the about 1V, about 50% of supply voltage and output current swing of about 0~200uA. Also, the power consumption was evaluated with about 21uW and the active size for an integration was measured with $71um{\times}166um$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.134-139
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• 2013

This paper describes design of a RF frequency synthesizer for the MBOA UWB systems with $0.13{\mu}m$ silicon CMOS technology. To generate effective clock signal of the MBOA novel technique which uses large scale multiplication in band of low frequency and small scale multiplication in band of high frequency has been used to reduce oscillation bandwidth of VCO. To get good performance of high speed and wide band operation characteristics a VCO using PMOS core structure and a frequency divider using super dynamic structure used in design of PLL circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.