• 한국산업정보학회논문지
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• 제12권2호
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• pp.79-84
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• 2007

본 논문에서는 CMOS를 이용한 온도 제어회로를 MOSIS의 0.25um-3.3V CMOS 설계규칙에 따라 설계하고 SPICE 시뮬레이션과 실험을 통하여 성능을 검토하였다. 설계된 회로는 $0^{\circ}C{\sim}150^{\circ}C$의 온도 범위에 대하여 출력 전압이 약 $13mV/^{\circ}C$로 변화하며 좋은 온도 선형성을 나타내었다. 또한, 바이어스 전압을 변화시키면 온도변화에 대한 출력전압의 변화량을 조정할 수 있다. 제안된 회로는 온 칩 수정발진회로의 설계 등에 유용하게 사용될 수 있을 것으로 기대된다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2004년도 추계학술대회 논문집
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• pp.809-813
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• 2004

In this paper, we developed a network camera for CMOS camera module inspection. The design, implementation details including embedded linux porting and CPLD logics, and performance of network camera are described. The network camera consists of SoC(S3C4530A), CPLD and CMOS image sensor. In order to image data of CMOS image sensor we designed capture logics on CPLD by using VHDL program. Embedded Linux such as uClinux is performed on the network camera to utilize development environment and TCP/IP protocol specification. The application is based on socket communication between GUI on PC and Embedded Linux based network camera. When JPEG compression is applied, the transmission speed was improved enough for this system to be used for an alternative of expensive CCTV or remote monitoring system in a power plant and uninhabited places.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1551_1552
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• 2009

In this paper, we presented the packaging technologies of CMOS ISFET(Ion Sensitive Field Effect Transistor) pH sensor using post-CMOS process and MCP(Multi Chip Packaging). We have proposed and developed two types of packaging technology. one is one chip, which sensing layer is deposited on the gate metal of standard CMOS ISFET, the other is two chip type, which sensing layer is separated from CMOS ISFET and connected by bonding wire. These proposed packaging technologies would make it easy to fabricate CMOS ISFET pH sensor and to make variety types of pH sensor.

• 전기학회논문지
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• 제56권7호
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• pp.1282-1287
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• 2007

We investigated the damage of the CMOS IC which manufactured three different technologies by high power microwave. The tests separated the two methods in accordance with the types of the CMOS IC located inner waveguide. The only CMOS IC which was located inner waveguide was occurred breakdown below the max electric field (23.94kV/m) without destruction but the CMOS IC which was connected IC to line organically was located inner waveguide and it was occurred breakdown and destruction below the max electric field. Also destructed CMOS IC was removed their surface and a chip condition was analyzed by SEM. The SEM analysis of the damaged devices showed onchuipwire and bondwire destruction like melting due to thermal effect. The tested results are applied to the fundamental data which interprets the combination mechanism of the semiconductors from artificial electromagnetic wave environment and are applied to the data which understand electromagnetic wave effects of electronic equipments.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술대회 논문집 전문대학교육위원
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• pp.113-116
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• 2003

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In this paper, proposes a method for efficiently generating test pattern which detect faults in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.517-518
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• 2008

Highly integrated ISFETs require the monolithic implementation of ISFETs, CMOS electronics, and additional sensors on the same chip This paper presents novel packaging type of CMOS ISFET pH sensor using standard CMOS FET chip and extended sensing membrane which is separated from CMOS FET. This proposed packaging type will make it easy to fabricate CMOS ISFET pH sensors

• 전자공학회논문지C
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• 제35C권12호
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• pp.40-48
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• 1998

본 논문에서는 rail-to-rail 복합입력단을 갖는 증폭회로의 옵셋전압을 보상해주기 위한 방법을 제안하고 집적회로로 구현하였다. 두 개의 보조증폭회로와 옵셋보상 커패시터들을 사용하여 NMOS 차동쌍과 PMOS 차동쌍의 옵셋을 각각 보상하고, ping-pong control을 사용하여 연속시간 동작이 가능한 3V rail-to-rail CMOS 증폭회로를 설계하였다. 설계된 증폭회로를 0.8㎛ single-poly double metal CMOS 공정으로 제작한 후 성능을 측정한 결과, 옵셋보상후의 옵셋전압은 옵셋보상전에 비해 약 20배정도 감소하였다.

• 대한전자공학회논문지
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• 제26권9호
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• pp.1359-1368
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• 1989

In this paper, the composite BiCMOS transistor which combines a bipolar transistor and a MOS transistor in a cascade type, is analyzed in terms of I-V characteristics and small signal equivalent circuit. As a result, it has a larger driving capability than MOS transistor and a more extended rante of input voltage than bipolar transistor. Next, a BiCMOS differential amplifier as its application example is designed and compared with the CMOS one and the bipolar one. It increases the driving capability of the CMOS differential amp and improves the linear operation region of the bipolar differential amp.

• 한국지능시스템학회:학술대회논문집
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• 한국지능시스템학회 2008년도 춘계학술대회 학술발표회 논문집
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• pp.247-250
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• 2008

최근 무선통신용 LSI는 배터리 수명과 관련하여, 저전력 동작이 중요시되고 있다. 따라서 Digital CMOS 신호처리와 더불어 동작 가능한 SI (Switched-Current) circuit를 이용하는 Current-mode 신호처리가 주목받고 있다. 그러나 SI circuit의 기본인 Current Memory는 Charge Injection에 의한 Clock Feedthrough라는 문제점을 갖고 있기 때문에, 전류 전달에 있어서 오차를 발생시킨다. 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 해결방안으로 CMOS Switch의 연결을 검토하였고, 0.25${\mu}m$ CMOS process에서 Memory MOS와 CMOS Switch의 Width의 관계는 simulation 결과를 통하여 확인하였으며, MOS transistor의 관계를 분명히 하여, 설게의 지침을 제공한다.

• 대한전자공학회논문지
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• 제22권5호
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• pp.50-56
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• 1985

A common failure mechanism in bulk CMOS integrated circuits is the latch-up of parasitic SCR structure inherent in the bulk CMOS structure. Latch-up triggering and holding charac-teristics have been measured in the test devicrs which include conventional and Schottky-damped CMOS structures with various well depths and n+/p+ spacings. It is demonstrated that Schottky-clamped CMOS is more latch-up immune than conventional bulk CMOS. Finally, the simulation results by circuit simulation program (SPICE) are compared with measured results in order to verify the validity of the latch-up modal composed of nan, pnp transistors and two external resistors.