• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.1
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• pp.660-665
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• 2018

Research into underwater wireless networks that enable the monitoring and controlling of the ocean environments has been continuing for disaster prevention and military proposes, as well as for the exploitation of ocean resources throughout the world. A research group led by Hoseo university has been studying a distributed underwater monitoring and controlling network. In this study, we developed an interpolator for acoustic communication between an underwater base station controller and underwater base station, which is included in this network. The underwater acoustic communication provided by this network defines four links whose sampling rates are different. Low power consumption is one of the most important requirements. Therefore, we adopted CIC interpolators, which are known to act as filters with a low power consumption, and some CIC interpolators with an appropriate changing rate were selected depending on the link. However, these interpolators have a large passband drop and wide transition region. To solve these problems, we added a compensator and half-band filter. After verifying the algorithm by using Matlab, we designed and verified it with Verilog-HDL in a ModelSim environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1785-1792
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• 2000

In this paper multi-rate non-recursive architecture for CIC(Cascaded Integrator-Comb) decimation filters with an arbitrary factor is proposed. The CIC filters are widely used in high speed wireless communication systems since they have multiplier-less and multi-rate low-power structure. Even conventional non-recursive CIC structure is multi-rate this architecture can be structured only in case of M-th power-of-two decimation factor. This paper proposes that muli-rate non-recursive CIC architecture can be structured with an any decimation factor of product form. Power consumption of the proposed architecture is compared with that of the conventional non-recursion architecture.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.6
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• pp.1-8
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• 2011

Power Line Communication (PLC: Power Line Communication) to propagate the current power lines are in every household of the existing infrastructure is the most extensive network configuration. In addition, the cost required for network configuration, the advantage of almost zero for the investors and is sufficient to attract the attention of operators. The PLC is supply power to power lines used the voice and data communication technologies put it on KHz ~ tens of hundreds of high-frequency signal MHz. But because uses power lines as existing wireless communications systems will occurs interference. The notch filters of a common way to eliminate the interference are used. In this paper, a dynamic high-performance notch filter applying CIC filter performance was verified through MATLAB and was implemented using a TI's TMS320C6416T DSP board.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.2
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• pp.111-117
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• 2004

The low-power design of the A/D converter is indispensable to achieve the compact bio-signal measuring device with long battery duration. In this paper, new decimation filter structure is proposed for the low-power design of the Sigma-Delta A/D converter in the bio-instruments. The proposed filter is based on the non-recursive structure of the CIC (Cascaded Integrator Comb) decimation filter in the Sigma-Delta A/D converter. By combining the CSD (Canonic Signed Digit) structure with common sub-expression sharing technique, the proposed decimation filter structure can significantly reduce the number of adders for implementation. For the fixed decimation factor of 16, the 15％ of power consumption saving is achieved in the proposed structure in comparison with that of the conventional polyphase CIC filter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1687-1694
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• 2011

In this paper, we propose the design procedure of a digital IF system for the OFDM based WLAN system and examine its performances. Along with the decision procedure of ADC sample rate, NCO frequency and the required decimation ratio, we show the decimation ratio is accomplished through the use of a CIC filter and a MHBF. We also show that the amplitude distortion occurred in the decimation filters can effectively be compensated by a ISOP filter and an additional FIR filter, which leads to the reduction of the overall hardware complexity. Finally, we examine the BER performance of the proposed system and compare it with a theoretical one that excludes filter non-linearities.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.3
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• pp.11-17
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• 2010

Multi-standard, multi-band, multi-service system to ensure a flexible interface between the SDR (Software Defined Radio) technology for the implementation of the Stability and Low-Power, Low-Calcualrion DDC (Digital Down Conversion) technology is essential. DDC technology consists of a digital channel filter. This is a typical digital filter because of the limited fisheries are vulnerable to overflow and rounding errors are drawbacks. In this paper, we overcome this disadvantage, we propose the structure of the DDC. The way WDF (Wave Digital Filter) Structural rounding error due to the structural resistance to noise. Therefore, This is the useful structure when the filter coefficients's word length is short. In addition, since IIR filters based on FIR filters based on the amount of computation is reduced because fewer than filter's tap. The proposed structure is used in DDC that CIC (Cascaded Integrator Comb) filter, WDF, IFOP (Interpolated Fourth-Order Polynomials) were analyzed with respect to, the results were confirmed by computer simulation.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.3
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• pp.405-412
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• 2010

The purpose of this paper is to compare complexity and to assess flexibility of competing transponder architectures for satellite communication services. For performance comparison, we consider three channelization techniques: digital down converter(DDC) based on the use of the cascaded integrator-comb(CIC) filter, tuneable pipeline frequency transform(T-PFT) based on the tree-structure(TS) and variable oversampled complex-modulated filter banks(OCM-FB) based on the polyphase FFT(P-FFT). The comparison begins by presenting a basic architecture of each channelization method and includes analytical expressions of the number of multiplications as a computational complexity perspective. The analytical results show that DDC with CIC filter requires the heavy computational burden and the perfect flexibility. T-PFT based on the TS provides the almost perfect flexibility with the low complexity over DDC with the CIC filter for a large number of sub-channels. OCM-FB based on the P-FFT shows the high flexibility and the best computational complexity performance compared with other approaches.

• Journal of Satellite, Information and Communications
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• v.5 no.1
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• pp.32-37
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• 2010

The algorithm of multiple channel signal processing requires the flexibility of variable frequency band, efficient allocation of transmission power, and flexible frequency band reallocation to satisfy various service types which requires different transmission rates and frequency band. There are three methods including per-channel approach, multiple tree approach, and block approach performing frequency band reallocation method by channelization and dechannelization in the multiple-channel signal. This paper proposes an improved per-channel approach for converting the frequency band of multiple carrier signals efficiently. The proposed algorithm performs decimation and interpolation using CIC(cascaded integrator comb filter), half-band filter, and FIR filter. In addition, it performs filtering of each sub-channel, and reallocates channel band through FIR low-pass filter in the multiple-channel signal. The computer simulation result shows that the perfect reconstruction of output signal and the flexible frequency band reallocation is performed efficiently by the proposed algorithm.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.951-954
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• 2001

본 논문에서는 SDR (Software Defined Radio)시스템을 위한 디지털 IF (Intermediate Frequency)수신기를 구현하였다[1][2]. 구현된 수신기의 하드웨어 구조는 AD변환부, PDC(Programmable Down Converter)부, DSP (Digital Signal Processing)부분으로 이루어졌다. AD변환부는 Analog Devices사의 AD6644를 이용하여 아날로그 신호를14bit의 디지털 신호로 변환된다. PDC부분은 Intersil사의 HSP 50214B를 이용하여 14bit 샘플 된 IF(Intermediate Frequency)입력을 혼합기와 NCO(Numerically Controlled Oscillator)에 의해 기저대역으로 다운 시키는 역할을 한다. PDC는 CIC (Cascaded Integrator Comb)필터, Halfband 필터 그리고 프로그램할 수 있는 FIR필터로 구성되어 있다. 그리고 PDC부분을 제어하고 PDC부분에서 처리할 수 없는 캐리어, 심볼 트래킹을 위해 Texas Instrument사의 16비트의 고정소수점 DSP인 TMS320C5416과 Altera사의 FPGA를 사용하였다. 그러므로 중간주파수 대역과 기저대역 간의 신호변환을 디지털 신호처리를 수행함으로써 일반적인 아날로그 처리방식보다 고도의 유연성과 고성능 동작이 가능하고 시간과 환경 변화에 우수한 동작 특성을 제공한다.