• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.7-12
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• 2018

The effects of Ru deposition temperature and post-annealing conditions on the interfacial adhesion energies of atomic layer deposited (ALD) Ru diffusion barrier layer and Cu thin films for the advanced Cu interconnects applications were systematically investigated. The initial interfacial adhesion energies were 8.55, 9.37, $8.96J/m^2$ for the sample deposited at 225, 270, and $310^{\circ}C$, respectively, which are closely related to the similar microstructures and resistivities of Ru films for ALD Ru deposition temperature variations. And the interfacial adhesion energies showed the relatively stable high values over $7.59J/m^2$ until 250h during post-annealing at $200^{\circ}C$, while dramatically decreased to $1.40J/m^2$ after 500 h. The X-ray photoelectron spectroscopy Cu 2p peak separation analysis showed that there exists good correlation between the interfacial adhesion energy and the interfacial CuO formation. Therefore, ALD Ru seems to be a promising diffusion barrier candidate with reliable interfacial reliability for advanced Cu interconnects.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.65-73
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• 2003

This paper presents the implementation of an analog signal-processing ASIS to detect an angular velocity signal from a vibrator angular velocity detection sensor. The output of the sensor to be charge appeared as the variation of the capacitance value in the structure of the sensor was detected using charge amplifiers and a self oscillation circuit for driving the sensor was implemented with a sinusoidal self oscillation circuit using the resonance characteristics of the sensor. Specially an automatic gain control circuit was utilized to prevent the deterioration of self-oscillation characteristics due to the external elements such as the characteristic variation of the sensor process and the temperature variation. The angular velocity signal, amplitude-mod)Hated in the operation characteristics of the sensor, was demodulated using a synchronous detection circuit. A switching multiplication circuit was used in the synchronous detection circuit to prevent the magnitude variation of detected signal caused by the amplitude variation of the carrier signal. The ASIC was designed and implemented using 0.5${\mu}{\textrm}{m}$ CMOS process. The chip size was 1.2mm x 1mm. In the experiment under the supply voltage of 3V, the ASIC consumed the supply current of 3.6mA and noise spectrum density from dc to 50Hz was in the range of -95 dBrms/√Hz and -100 dBrms/√Hz when the ASIC, coupled with the sensor, was in normal operation.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.11-20
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• 1999

The data transfer width between the mocroprocessor and the memory comes to a critical part that limits system performance since the data transfer width has been as it was while the performance of a microprocessor is getting higher due to its continuous development in speed. And it is important that the memory should be in small size for the reduction of embedded microprocessor's price which is integrated on a single chip with the memory and IO circuit. In this paper, a mocroprocessor tentatively named as Extendable Instruction Set Computer(EISC) is proposed as the high code density 32 bit mocroprocessor architecture. The 32 bit EISC has 16 general purpose registers and 16 bit fixed length instruction which has the short length offset and small immediate operand. By using and extend register and extend flag, the offset and immediate operand could be extended. The proposed 32 bit EISC is implemented with an FPGA and all of its functions have been tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit EISC shows 140-220% and 120-140% higher code density than RISC and CISC respectively, which is much higher than any other traditional architectures. As a consequence, the EISC is suitable for the next generation computer architecture since it requires less data transfer width compared to any other ones. And its lower memory requirement will embedded microprocessor more useful.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.4
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• pp.55-62
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• 2004

In this paper, we have developed a portable acceleration measurement system to measure acceleration signals during walking and a gait analysis algorithm which can evaluate gait regularity and symmetry and estimate gait parameters automatically. Portable acceleration measurement system consists of a biaxial accelerometer, amplifiers, lowpass filter with cut-off frequency of 16Hz, one-chip microcontroller, EEPROM and RF(TX/RX) module. The algerian includes FFT analysis, filter processing and detection of main peaks. In order to develop the algorithm, eight hemiplegic patients for training set and the other eight hemiplegic patients for test set are participated in the experiment. Acceleration signals during 10m walking were measured at 60 samples/sec from a biaxial accelerometer mounted between L3 and L4 intervertebral area. The algorithm, detected foot contacts and classified right/left steps, and then calculated gait parameters based on these informations. Compared with video data and analysis by manual, algorithm showed good performance in detection of foot contacts and classification of right/left steps in test set perfectly. In the future, with improving the reliability and ability of the algerian so that calculate more gait Parameters accurately, this system and algerian could be used to evaluate improvement of walking ability in hemiplegic patients in clinical practice.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.3
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• pp.50-56
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• 2010

In this paper, compact broad-band antenna using circular spiral slot and CPW (coplanar waveguide) feed is proposed. The proposed antenna is designed on the same plane of the substrate by using CPW fed structure, archimediean spiral slot structure. So it was achieved both the size of compact antenna and the broad band. A archimediean spiral slot structure is introduced for resonance of medium band operation. The distances of a CPW feeder line and a ground plane are modified for impedance matching and lower/higher band operation. The proposed antenna has a compact size ($8mm\;{\times}\;13mm$) and it is etched on the FR-4 (relative dielectric constant 4.4, thickness 0.8mm) dielectric substrate. The simulated impedance bandwidth (VSWR $\leq$ 2) and maximum gain of the proposed antenna are 5.98GHz (4.1GHz ~ 10.08GHz) and 3.97dBi, respectively. The measured impedance bandwidth (VSWR $\leq$ 2) and maximum gain of the proposed antenna are 6.02GHz (4.48GHz ~ 10.5GHz) and 2.68dBi, respectively. The simulation and measured result shows good impedance matching and radiation pattern over the interesting frequency bands. It can be applied to antenna of broad-band wireless communication system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.75-87
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• 2010

For two input-protection schemes suitable for RF ICs utilizing the thyristor and diode protection devices, which can be fabricated in standard CMOS processes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit for an input HBM test environment of a CMOS chip equipped with the input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain the characteristic differences of two protection schemes as an input ESD protection circuit for RF ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.62-68
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• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.15-21
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• 2011

In this paper, an energy management circuit for solar energy harvesting system is designed in $0.35{\mu}m$ CMOS technology. The solar energy management system consists of an ISC(Integrated Solar Cell), a voltage booster, and an MPPT(Maximum Power Point Tracker) control unit. The ISC generates an open circuit voltage of 0.5V and a short circuit current of $15{\mu}A$. The voltage booster provides the following circuit with a supply voltage about 1.5V. The MPPT control unit turns on the pMOS switch to provide the load with power while the ISC operates at MPP. The SEMU(Solar Energy Management Unit) area is $360{\mu}m{\times}490{\mu}m$ including pads. The ISC area is $500{\mu}m{\times}2000{\mu}m$. Experimental results show that the designed SEMU performs proper MPPT control for solar energy harvested from the ISC. The measured MPP voltage range is about 370mV∼420mV.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.4
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• pp.1-9
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• 2012

LCD(Liquid Crystal Display) commonly used as an output device has a drawback of slow response time compared with CRT display. This drawback causes motion blur especially when an abrupt intensity change occurs in an image sequence as time goes on. To overcome the problem of slow response time overdriving technique has been used in TCON of LCD. In this technique, the previous frame data has to be compressed and stored in an external memory. Considering both chip size of TCON and computational complexity, AM-BTC has been applied to the 8bit HD display driver. However, the conventional method is not suitable for 10 bit Full HD because 10 bit Full HD data is much larger than that of 8 bit HD data. Being applied to 10 bit Full HD display driver, the conventional method increase cost by enlarging the external memory size of TCON or deteriorates image quality. In this paper, we propose dual BTC image coding technique for Full HD display driver that is an adaptive coding scheme according to morphological information of each sample block. Through experiments, it is verified that the proposed Dual BTC method performs better than the conventional method not only quantitatively but also qualitatively.