• KSBB Journal
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• v.16 no.6
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• pp.603-608
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• 2001

In this study, we studied on the remeval of toluene vapors in a lab-scale biofilter. Biofiltration was performed in a column fed downflow with contaminated air at ambient conditions. The column was packed with mixture of Peat and Calstene(5:3 vol. Ratio), Synthesized media, Bark and Wood chip, which were inoculated with microbial population of selected stains(Pseudomonas. putida, KCCM 11343, ATCC 12633). The microorganisms were immobilized on the bed medium and then biofilm were formed. The biofilter was operated under the conditions of various inlet toluene concentrations for 180 days and treated up to the elimination capacity of maximum 40 g/㎥hr at the inlet load of 30 g/㎥ hr with percentage removals of 20∼90% and gas retention times between 1 and 2 min. The pressure drop was very negligible through the biofilter columps because its value of 0.054 cmH$_2$O/m was much less than others. The effect of operating conditions such as flow rate, inlet toluene concentration and moisture contents on the performance of the biofilter was sequentially investigated in this study.

• 전기의세계
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• v.43 no.1
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• pp.13-19
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• 1994

전자식 안정기는 최근 에너지 절약 정책과 관련하여 조명기기분야의 관심의 대상이 되었고, 절전 효율이 높은 고품질의 전자식 안정기에 대한 연구 개발 및 보급이 점점 더 확대되고 있는 추세이다. 일반적으로 전자식 안정기는 수십 KHz의 고주파에서 형광등을 구동시킴으로써 빛의 깜박거림과 가청잡음이 없으며, 저주파(60Hz)에서 사용하는 재래식 안정기(choke coil 방식)에 비해 높은 절전 효과를 얻을 수 있다[1-4]. 특히, 빌딩 사무실의 경우 낮에도 창가의 형광등이 켜져 있어서 막대한 전력을 낭비하고 있는 실정이므로, 일조량에 따른 자동 전력 조절이 가능한 전자식 형광등의 출현이 기대되고 있다. 전자식 안정기의 보급 확대를 위해서는 절전 효과 뿐만 아니라, 품질 문제, 수명 문제등을 고려하여야 하는 바, 예를 들면 순간 점등으로 방전초기의 sputtering 현상에 의한 lamp의 수명 단축, 미소 입력전압 변동에 따른 급격한 광출력의 변화로 절전 효과의 상실과 이상동작에 의한 스위칭 소자의 파괴 현상, 고주파 스위칭시 발생되는 전력손실과 noise등에 대한 대책이 요구되고 있다. 이러한 점을 개선하기 위해 추가되는 회로는 전자식 안정기 시스템을 더욱 복잡하게 만들고, 경제적으로 원가 부담을 주기 때문ㅇ 고품질의 전자식 안정기를 보급하는데 어려운 점으로 부각되고 있다. 본 고에서는 이러한 문제를 해결하기 위하여 조광기능을 포함한 다양한 제어회로와 보호회로를 조광기능을 포함한 다양한 제어회로와 보호회로를 1 chip에 수용하는 고품질의 전자식 안정기 제어용 집적회로에 대해서 기술하고자 한다.되어 나아갈 기술의 조류에도 부합하는 형태라 하겠다. 그러나 이 방식은 기 언급한 바와 같이 분산처리를 관장하는 운영체계의 개발에 상당한 고전이 따르리라 보여지며, 또한 보다 상세한 연구가 선행되어야 하겠지만 개발된 상용의 통신 프로토콜로서는 병렬처리의 성능을 극대화 하기에는 여러가지 제약이 있을 것으로 예측된다.기기들이 어떻게 응용되고 있는지 살펴보기로 하자. real informations would be available. Results are compared with those of optimal power flows.기능시험을 완료했으며 실제 line-of-sight(LOS) 시스템 구현에 적용중이다. 시대를 살아 갈 회원들이다. '컨텐츠의 시대'가 개막되는 것이며, 신세기통신과 SK텔레콤은 선의의 경쟁 과 협력을 통해 이동인터넷 서비스의 컨텐츠를 개발해 나가게 될 것이다. 3배가 높았다. 효소 활성에 필수적인 물의 양에 따른 DIAION WA30의 라세미화 효율에 관하여 실험한 결과, 물의 양이 증가할수록 그 효율은 감소하였다. DIAION WA30을 라세미화 촉매로 사용하여 아이소옥탄 내에서 라세믹 나프록센 2,2,2-트리플로로에틸 씨오에스터의 효소적 DKR 반응을 수행해 보았다. 그 결과 DIAION WA30을 사용하지 않은 경우에 비해 반응 전환율과 생성물의 광학 순도는 급격히 향상되었다. 전통적 광학분할 반응의 최대 50%라는 전환율의 제한이 본 연구에서 찾은 DIAION WA30을 첨가함으로써 성공적으로 극복되었다. 또한 고체 염기촉매인 DIAION WA30의 사용은 라세미화 촉매의

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.2
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• pp.74-80
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• 2017

This study focuses on the effects of doping $Zn_2BiVO_6$ and $Co_3O_4$ on the sintering and electrical properties of ZnO; where, ZZ consists of 0.5 mol% $Zn_2BiVO_6$ in ZnO, and ZZCo consists of 1/3 mol% $Co_3O_4$ in ZZ. As ZnO was sintered at about $800^{\circ}C$, the liquid phases, which are composed of $Zn_2BiVO_6$ and $Zn_2BiVO_6$-rich phases, were found to be segregated at the grain boundaries of sintered ZZ and ZZCo, respectively, which demonstrates that $V_o^{\cdot}$(0.33~0.36 eV) are formed as dominant defects according to the analysis of admittance spectroscopy. As $Co_3O_4$ is doped to ZZ, the resistivity of ZnO decreases to ~38%, while donor density ($N_d$), interface state density ($N_t$), and barrier height (${\Phi}_b$) increase twice higher than those of ZZ, according to C-V characteristics. This result harbingers that ZZCo and its derivative compositions will open the gate for ZnO to be applied as more progressive varistors in the future, as well as the advantageous opportunity of manufacturing ZnO chip varistors at lower sintering temperatures below $900^{\circ}C$.

• Journal of the Korea Convergence Society
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• v.8 no.5
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• pp.161-167
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• 2017

We have fabricated and characterized $32{\times}32$ photonic quantum ring (PQR) laser arrays uniformly operable with $0.98{\mu}A$ per ring at room temperature. The typical threshold current, threshold current density, and threshold voltage are 20 mA, $0.068A/cm^2$, and 1.38 V. The top surface emitting PQR array contains GaAs multiquantum well active regions and exhibits uniform characteristics for a chip of $1.65{\times}1.65mm^2$. The peak power wavelength is $858.8{\pm}0.35nm$, the relative intensity is $0.3{\pm}0.2$, and the linewidth is $0.2{\pm}0.07nm$. We also report the wavelength division multiplexing system experiment using angle-dependent blue shift characteristics of this laser array. This photonic quantum ring laser has angle-dependent multiple-wavelength radial emission characteristics over about 10 nm tuning range generated from array devices. The array exhibits a free space detection as far as 6 m with a function of the distance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.93-100
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• 2009

This paper presents a step up four channel DC-DC converter using charge pump voltage doubler structure. Our goal is to design and implement DC-DC converter for capacitive SP4T RF MEMS switch in front end module in wireless transceiver system. Charge pump structure is small and consume low power 3.3V input voltage is boosted by DC-DC Converter to $11.3{\pm}0.1V$, $12.4{\pm}0.1V$, $14.1{\pm}0.2V$ output voltage With 10MHz switching frequency. By using voltage level shifter structure, output of DC-DC converter is selected by 3.3V four channel selection signals and transferred to capacitive MEMS devices. External passive devices are not used for driving DC-DC converter. The total chip area is $2.8{\times}2.1mm^2$ including pads and the power consumption is 7.52mW, 7.82mW, 8.61mW.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.1
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• pp.77-83
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• 2011

In this thesis, 50W Doherty amplifier was designed and implemented for Beyond 3G's repeater and base-station. Auxiliary amplifier of doherty amplifier was implemented by Gate bias control circuit. Though gate bias control circuit solved auxiliary's bias problem, output characteristics of doherty amplifier was limited. To enhance the output characteristic relativize Drain control circuit And To improve power efficiency make 3-way Doherty power amplifier. therefore, 3-way GDCD (Gate and Drain bias Control Doherty) power amplifier is embodied to drain bias circuit for General Doherty power amplifier. The 3-way GDCD power amplifier composed of matching circuit with chip capacitor and micro strip line using FR4 dielectric substance of specific inductive capacity(${\varepsilon}r$) 4.6, dielectric substance height(H) 30 Mills, and 2.68 Mills(2 oz) of copper plate thickness(T). Experiment result satisfied specification of amplifier with gains are 57.03 dB in 2.11 ~ 2.17 GHz, 3GPP frequency band, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and ACLR characteristics at 5MHz offset frequency band station is -40.45 dBc. Especially, 3-way DCHD power amplifier showed excellence efficiency performance improvement in same ACLR than general doherty power amplifier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.96-106
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• 2014

Previous academic research on FPGA tools has relied on simple imaginary models for the targeting architecture. As the first step to overcome such restriction, the issues on analytic placement and legalization which are applied to commercial FPGAs have been brought up, and several techniques to remedy them are presented, and evaluated. First of all, the center of gravity of the placed cells may be far displaced from the center of the chip during analytic placement. A function is proposed to be added to the objective function for minimizing this displacement. And then, the density map is expanded into multiple layers to accurately calculate the density distribution for each of the cell types. Early fixation is also proposed for the memory blocks which can be placed at limited sites in small numbers. Since two flip-flops share control pins in a slice, a compatibility constraint is introduced during legalization. Pre-packing compatible flip-flops is proposed as a proactive step. The proposed techniques are implemented on the K-FPGA fabric evaluation framework in which commercial architectures can be precisely modeled, and modified for enhancement, and validated on twelve industrial strength examples. The placement results show that the proposed techniques have reduced the wire length by 22%, and the slice usage by 5% on average. This research is expected to be a development basis of the optimization CAD tools for new as well as the state-of-the-art FPGA architectures.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.80-86
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• 2014

A low-noise readout circuit is studied for 2-D capacitive microbolometer focal plane arrays (FPAs). In spite of the merits of the integration method, a simple and effective pixelwise readout circuit without integration is used for input circuit because of a small pixel size and narrow noise bandwidth. To reduce the power consumption and the kT/C noise, which is the dominant noise of the capacitive microbolometer FPAs with small capacitance, a new correlated double sampling (CDS) is used for columnwise circuit. The proposed circuit has been designed using a $0.35-{\mu}m$ 2-poly 4-metal CMOS process for a microbolometer array with a pixel size of $50{\mu}m{\times}50{\mu}m$. The proposed circuit effectively reduces the kT/C noise and the other low-frequency noise of microbolometer, and the noise characteristics of the fabricated chip have been verified by measurements. The rms noise voltage of the proposed circuit is reduced from 30 % to 55 % compared to that of the simple readout input circuit, and the noise equivalent temperature difference (NETD) of the proposed circuit is very low value of 21.5 mK.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.