Browse > Article
http://dx.doi.org/10.5573/ieie.2014.51.10.096

Pre-Packing, Early Fixation, and Multi-Layer Density Analysis in Analytic Placement for FPGAs  

Kim, Kyosun (Department of Electronic Engineering, Incheon National University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.10, 2014 , pp. 96-106 More about this Journal
Abstract
Previous academic research on FPGA tools has relied on simple imaginary models for the targeting architecture. As the first step to overcome such restriction, the issues on analytic placement and legalization which are applied to commercial FPGAs have been brought up, and several techniques to remedy them are presented, and evaluated. First of all, the center of gravity of the placed cells may be far displaced from the center of the chip during analytic placement. A function is proposed to be added to the objective function for minimizing this displacement. And then, the density map is expanded into multiple layers to accurately calculate the density distribution for each of the cell types. Early fixation is also proposed for the memory blocks which can be placed at limited sites in small numbers. Since two flip-flops share control pins in a slice, a compatibility constraint is introduced during legalization. Pre-packing compatible flip-flops is proposed as a proactive step. The proposed techniques are implemented on the K-FPGA fabric evaluation framework in which commercial architectures can be precisely modeled, and modified for enhancement, and validated on twelve industrial strength examples. The placement results show that the proposed techniques have reduced the wire length by 22%, and the slice usage by 5% on average. This research is expected to be a development basis of the optimization CAD tools for new as well as the state-of-the-art FPGA architectures.
Keywords
FPGA; Analytic Placement; Multi-Layer Density Analysis; Pre-Packing; Early Fixation;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 K. Kim, "Evaluation Toolkit for K-FPGA Fabric Architectures," Journal of the IEEK, vol. 49-SD, no. 4, pp.157-167, April, 2012.
2 ABC: A System for Sequential Synthesis and Verification. Berkeley Logic Synthesis and Verification Group, http://www.eecs.berkeley.edu/-alanmi/abc/abc.html, October, 2007.
3 V. Betz and J. Rose, "VPR: A New Packing, Placement And Routing Tool For FPGA Research," in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications. pp.213-222, 1997.
4 K. Kim, "Fabric Mapping and Placement of Field Programmable Stateful Logic Array," Journal of the IEEK, vol. 49, no. 12, pp. 1067-1076, December, 2012.
5 N. Steiner, A. Wood, H. Shojaei, J. Couch, P. Athanas, M. French, "Torc: Towards Open-Source Tool Flow," in Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp.41-44, February, 2010.
6 C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson, and B. Hutchings, "RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs" in Proceedings of the 21st International Workshop on Field-Programmable Logic and Applications, pp.349-355, September, 2011.
7 Spartan-3 Generation FPGA User Guide, UG331, v1.6, Xilinx Inc., December 3, 2009.
8 W.C. Naylor, R. Donelly, and L. Sha, "Non-Linear Optimization System and Method for Wire Length and delay Optimization for an Automatic Electric Circuit Placer," US Patent 6301693, October 2001.
9 J. Cong and G. Luo, "Highly Efficient Gradient Computation for Density-Constrained Analytical Placement Methods," Proc. of the International Symposium on Physical Design, pp. 39-45, April, 2008.
10 D.J.C. MacKay, "MacOpt-a Nippy Wee Optimizer," http://www.inference.phy.cam.ac.uk/mackay/c/macopt.html, June, 2004.
11 Xilinx Design Language Version 1.6, Xilinx, Inc., Xilinx ISE 6.1i Documentation in ise6.1i/help/data /xdl, July 2000.
12 X. Song, "Smoothing Method for Minimax Problems," Computational Optimization and Applications, Kluwer Academic Publishers, 20, pp.267-279, 2001.