• Journal of the Institute of Convergence Signal Processing
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• v.13 no.2
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• pp.83-90
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• 2012

In this paper, an intelligent visual surveillance system based on a NIOS II embedded platform is implemented. By this time, embedded based visual surveillance systems were restricted for a special purpose because of high dependence upon hardware. In order to improve the restriction, we implement a flexible embedded platform, which is available for various purpose of applications. For high speed processing of software based programming, we improved performance of the system which is integrated the SOPC type of NIOS II embedded processor and image processing algorithms by using software programming and C2H(The Altera NIOS II C-To-Hardware(C2H) Acceleration Compiler) compiler in the core of the hardware platform. Then, we constructed a server system which globally manage some devices by the NIOS II embedded processor platform, and included the control function on networks to increase efficiency for user. We tested and evaluated our system at the designated region for visual surveillance.

• Electronics and Telecommunications Trends
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• v.36 no.2
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• pp.32-42
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• 2021

The rapid growth of deep-learning applications has invoked the R&D of artificial intelligence (AI) processors. A dedicated software framework such as a compiler and runtime APIs is required to achieve maximum processor performance. There are various compilers and frameworks for AI training and inference. In this study, we present the features and characteristics of AI compilers, training frameworks, and inference engines. In addition, we focus on the internals of compiler frameworks, which are based on either basic linear algebra subprograms or intermediate representation. For an in-depth insight, we present the compiler infrastructure, internal components, and operation flow of ETRI's "AI-Ware." The software framework's significant role is evidenced from the optimized neural processing unit code produced by the compiler after various optimization passes, such as scheduling, architecture-considering optimization, schedule selection, and power optimization. We conclude the study with thoughts about the future of state-of-the-art AI compilers.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.1
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• pp.13-19
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• 2011

In this paper, a visual surveillance system using SOPC based NIOS II embedded processor and C2H compiler was implemented. In this system, the IP is constructed by C2H compiler for the output of the camera images, image processing, serial communication and network communication, then, it is implemented to effectively control each IP based on the SOPC and the NIOS II embedded processor. And, an algorithm which updates the background images for high speed and robust detection of the moving objects is proposed using the Adaptive Gaussian Mixture Model(AGMM). In results, it can detecte the moving objects(pedestrians and vehicles) under day-time and night-time. It is confirmed that the proposed AGMM algorithm has better performance than the Adaptive Threshold Method(ATM) and the Gaussian Mixture Model(GMM) from our experiments.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.4
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• pp.580-585
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• 2010

In this paper, The object Tracking System is designed by SOPC based Nios II embedded processor and C2H compiler. And this system using single PTZ camera can effectively control IPs in the platform of SOPC based Nios II Embedded Processor and creating IP by C2H(C-To-Hardware) compiler for image-in/output, image-processing and devices of communication that can supply various monitoring information to network or serial. Accordingly, Special quality and processing speed of object tracking using high-quality algorism in the system is improved by hardware/software programming methods.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.639-645
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• 2015

Checksum and residue checking accelerators were implemented on a Nios II core-based platform according to component method, in which the corresponding hardware was implemented with HDL coding, a custom instruction method, in which the instruction set of the processor was extended, and the C2H method, in which the corresponding logic was automatically created by the C2H compiler. The processing results from each accelerator for each algorithm were then examined and compared. The results of the comparison showed that the accelerator implemented with the C2H method is the fastest in terms of the execution time, and the accelerator with custom instruction requires the least add-on from the viewpoint of add-on hardware.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• Proceedings of the KSR Conference
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• 2005.05a
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• pp.291-298
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• 2005

This paper describes the characteristic feather of propulsion system adopting mass production. The train formation is composed of 4 cars by 2 Motor cars and 2 Train cars. Acceleration rate must be 3.0 km/h/s or more when the car starts up to 35km/h by 16ton of passenger load. The system information supervision is easy because the system is controlled to perfect digital circuits, all information of an action is stored in a memory and is managed. The control system is composed of a fully digital circuit and a high level software such as C language. The DSP TMS320C31 is used for main processor and has the capability of 50MHz, 32bit floating point operation and has a C compiler. Therefore, the implementation of control algorithm and the change of function are easy. VVVF inverter using IGBT conducted variable combined test, environment test using chamber, interface test and field test etc.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.353-357
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• 2014

This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.

• Journal of Internet Computing and Services
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• v.8 no.4
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• pp.51-59
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• 2007

This paper presents the development of RFID educational system based on using 900MHz air interface between the reader and the active tag. The software of reader and the active tag is developed on embedded environment, and the software of PC controlling the reader is based on window OS operated as the server. The AT89C51ED2 VLSI chip is used for the processor of the reader and the active tag. As the development environment, Keil compiler is used for the reader and the active tag of which the programing language is C. The visual C language of the visual studio on the PC activated as the server is used for development language. To verify the function of the system, PC gets the tag's identification number through the reader and send the data to with the active tag memory a certain contents as "wite" operation. Finally the data written from the active tag's memory is sent to the PC via the reader as "read" operation and compare the received data with one already sent to the tag.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.1
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• pp.53-59
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• 2009

By the use of open source and 16bit Microcomputer, IDB(Integrated Development Board) for embedded technical education was designed and developed. Based on 16bit MCU H8/300H, LED, LED Matrix, motors, sensors and various I/O circuitry, and the connection to a computer via the SCI, and $16{\times}2$ character LCD was designed and implemented on IDB. In addition, the software development environment was build by the assembler and H8 C compiler which is provided to the open-source software. And memory expansion was considered to include TRON(Real time OS) and uClinux. To verify the developed board, IDB was fabricated by PCB machine, and the fuction was confirmed by the basic I/O control program.