• 한국전기전자재료학회논문지
• /
• 제15권4호
• /
• pp.301-307
• /
• 2002

Direct bonded SOI wafer pairs with $Si ll SiO_2/Si_3N_4 ll Si$ the heterogeneous insulating layers of SiO$_2$-Si$_3$N$_4$are able to apply to the micropumps and MEMS applications. Direct bonding should be executed at low temperature to avoid the warpage of the wafer pairs and inter-diffusion of materials at the interface. 10 cm diameter 2000 ${\AA}-SiO_2/Si(100}$ and 560 $\AA$- ${\AA}-Si_3N_4/Si(100}$ wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were pre- mated with facing the mirror planes by a specially designed aligner in class-100 clean room immediately. We employed a heat treatment equipment so called fast linear annealing(FLA) with a halogen lamp to enhance the bonding of pre mated wafers We kept the scan velocity of 0.08 mm/sec, which implied bonding process time of 125 sec/wafer pairs, by varying the heat input at the range of 320~550 W. We measured the bonding area by using the infrared camera and the bonding strength by the razor blade clack opening method, respective1y. It was confirmed that the bonding area was between 80% and to 95% as FLA heat input increased. The bonding strength became the equal of $1000^{\circ}C$ heat treated $Si ll SiO_2/Si_3N_4 ll Si$ pair by an electric furnace. Bonding strength increased to 2500 mJ/$\textrm{m}^2$as heat input increased, which is identical value of annealing at $1000^{\circ}C$-2 hr with an electric furnace. Our results implies that we obtained the enough bonding strength using the FLA, in less process time of 125 seconds and at lowed annealing temperature of $400^{\circ}C$, comparing with the conventional electric furnace annealing.

• 한국재료학회지
• /
• 제12권10호
• /
• pp.820-824
• /
• 2002

It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제4권3호
• /
• pp.196-203
• /
• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2010년도 춘계학술발표대회
• /
• pp.27.2-27.2
• /
• 2010

In recent years, there is a strong requirement of low cost, stable microelectro mechanical systems (MEMS) for resonators, microswitches and sensors. Most of these devices consist of freely suspended microcantilevers, which are usually made by the etching of some sacrificial materials. Herein, we have attempted to use Si nanowires, inherited from the parent Si wafer, as a sacrificial material due to its porosity, low cost and ease of fabrication. Prior to the fabrication of the Si nanowires silver nanoparticles were continuously formed on the surface of Si wafer. Vertically aligned Si nanowires were fabricated from the parent Si wafers by aqueous chemical route at $50^{\circ}C$. Afterwards, the morphological and structural characteristics of the Si nanowires were investigated. The morphology of nanowires was strongly modulated by the resistivity of the parent wafer. The 3-step etching of nanowires in diluted KOH solution was carried out at room temperature in order to control the fast etching. A layer of $Si_3N_4$ (300 nm) was used for the selective fabrication of nanowires. Finally, a freely suspended bridge of zinc oxide (ZnO) was fabricated after the removal of nanowires from the parent wafer. At present, we believe that this technique may provide a platform for the inexpensive fabrication of futuristic MEMS.

• 한국재료학회지
• /
• 제12권6호
• /
• pp.508-512
• /
• 2002

$2000{\AA}-SiO_2/Si(100)$ and $560{\AA}-Si_3N_4/Si(100)$ wafers, which are 10 cm in diameter, were directly bonded using a rapid thermal annealing method. We fixed the anneal time of 30 second and varied the anneal temperatures from 600 to $1200^{\circ}C$. The bond strength of bonded wafer pairs at given anneal temperature were evaluated by a razor blade crack opening method and a four-point bonding method, respectively. The results clearly slow that the four-point bending method is more suitable for evaluating the small bond strength of 80~430 mJ/$\m^2$ compared to the razor blade crack opening method, which shows no anneal temperature dependence in small bond strength.

• E2M - 전기 전자와 첨단 소재
• /
• 제9권7호
• /
• pp.727-732
• /
• 1996

In the present paper, the Cu films 4.mu.m thick were deposited by RF magnetron sputtering method on Si wafer. The Cu films deposited at a condition of 100W, 10mtorr exhibited a low electrical resistivity of 2.3.mu..ohm..cm and densed microstructure, poor adhesion. The Cu films grown by 200W, 20mtorr showed a good adhesion property and higher electrical resistivity of 7.mu..ohm..cm because of porous columnar microstructure. Therefore, The Cu films were deposited by double layer deposition method using RF magnetron sputtering on Si wafer. The dependence of the electrical resistivity, adhesion, and reflectance in the CU films [C $U_{4-d}$(low resistivity) / C $U_{d}$(high adhesion) / Si-wafer] on the thickness of d has been investigated. The films formed with this deposition methods had the low electrical resistivity of about 2.6.mu..ohm..cm and high adhesion of about 700g/cm.m.m.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
• /
• pp.370-373
• /
• 1999

Si direct bonding (SDB) technology is very attractive for both Si-on-insulator(SOI) electric devices and MEMS applications because of its stress free structure and stability. This paper presents on- pre treatment conditions in Si wafer direct bonding, The paper resents on pre-bonding according to HF pre-treatment conditions in Si wafer direct bonding. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, applied pressure and annealing temperature(200~ 100$0^{\circ}C$) after pre-bonding. The bonding strength was evaluated by tensile strength method. The bonded interface and the void were analyzed by using SEM and IR camera, respectively, Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding(Min 2.4kgf/$\textrm{cm}^2$~ Max : 14.kgf/$\textrm{cm}^2$)

• 센서학회지
• /
• 제12권6호
• /
• pp.265-272
• /
• 2003

본 논문은 파이렉스 #7740 유리 박막을 이용한 MEMS용 MLCA (Multi Layer Ceramic Actuator)와 Si기판의 양극접합 특성에 관한 것이다. 최적의 RF 마그네트론 스피터링 조건 (Ar 100%, input power $1\;W/cm^2$)하에서 MLCA기판위에 파이렉스 #7740 유리의 특성을 갖는 박막을 증착하였다. $450^{\circ}C$에서 1시간 열처리한 다음, -760 mmHg, 600V 그리고 $400^{\circ}C$에서 1시간동안 양극접합했다. 그 다음에 Si 다이어프램을 제조한 후, MLCA/Si 접합계면과 MLCA 구동을 통한 Si 다이어프램 변위특성을 분석 및 평가하였다. 다이어프램 형상에 따라 정밀한 변위 세어가 가능했으며 0.05-0.08 %FS의 우수한 선형성을 나타내었다. 또한, 측정동안 접합계면 균열이나 계면분리가 일어나지 않았다. 따라서, MLCA/Si기판 양각접합기술은 고성능 압전 MEMS 소자 제작공정에 유용하게 사용가능할 것이다.

• 한국재료학회지
• /
• 제14권5호
• /
• pp.315-321
• /
• 2004

The void evolution in direct bonding process of $Si/Si_3$$N_4$ ∥ $SiO_2$/Si silicon wafer pairs has been investigated with an infrared camera. The voids that formed in the premating process grew in the conventional furnace annealing process at a temperature of $600^{\circ}C$. The voids are never shrunken even with the additional annealing process at the higher temperatures. We observed that the voids became smaller and disappeared with sequential scanning by our newly proposed fast linear annealing(FLA). FLA irradiates the focused line-shape halogen light on the surface while wafer moves from one edge to the other. We also propose the void shrinking mechanism in FLA with the finite differential method (FDM). Our results imply that we may eliminate the voids and enhance the yield for the direct bonding of wafer pairs by employing FLA.

• 한국광학회:학술대회논문집
• /
• 한국광학회 2002년도 하계학술발표회
• /
• pp.46-47
• /
• 2002

Flame Hydrolysis Deposition (FHD) 공정은 SiC1$_4$, GeCl$_4$, POC1$_3$, BCl$_3$ 등의 원료를 사용하여 Si wafer 및 유리기판 위에 silicate soot를 증착하는 방법이며, 증착된 soot는 고온에서 소결과정을 거쳐 B$_2$O$_3$-P$_2$O$_{5}$ -GeO$_2$-SiO$_2$(BPGS)계 유리막으로 형성된다. 유리막의 굴절률은 SiC1$_4$, GeCl$_4$, POC1$_3$, BCl$_3$ 등의 원료 유량을 조절하여 변화가능하며 이를 이용하여 광도파로를 제작할 수 있다 특히 광통신에 사용할 수 있는 광증폭기 등의 능동형 광소자 제작을 위해서는 FHD공정을 통해 형성된 soot에 Er$^{3+}$ 등의 희토류 원소를 첨가하여야 한다. (중략)