• Proceedings of the Korea Crystallographic Association Conference
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• 2002.11a
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• pp.15-15
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• 2002

Homogeneous and crack-free potassium lithium niobate (K₃Li/sub 2-x/Nb/sub 5+x/O/sub 15/, 0＜x＜0.5, KLN) single crystals were successfully grown by the Czochralski technique. The KLN single crystals of several different compositions were employed for the investigation of the lattice vibration spectra using infrared Raman spectroscopy. The characteristic Raman spectra of the [NbO/sub 6/]/sup 7-/ octahedral ions were strikingly influenced by the Li ion content. The symmetric stretch vibrational modes V₁, V₂ are broadened, and the symmetric bend vibration mode V/sub 5/ is broadened and even split into three peaks with increasing the Li content, supporting that the bend vibration modes of the [NbO/sub 6/]/sup 7-/ octahedrons are obviously perturbed by Li ions in the C site. Enhanced Raman peak intensities after the post annealing at 900℃ and for 24 h evidenced that a residual stress in as-grown crystals was negligible and only a defect concentration might be reduced.

• Journal of the Korean Vacuum Society
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• v.17 no.3
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• pp.220-225
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• 2008

In this research, the P(VDF-TrFE) copolymer thin films were prepared by the physical vapor deposition and studied to their piezoelectric properties. In the case of a specimen produced by varying the deposition temperature from $260^{\circ}C$ to $300^{\circ}C$, its piezoelectric coefficient($d_{33}$) increased from 32.3pC/N to 36.28pC/N, and piezoelectric voltage coefficient($g_{33}$) from $793{\times}10^{-3}V{\cdot}m/N$ to $910.5{\times}10^{-3}V{\cdot}m/N$. On the basis of these experimental results, we concluded that the P(VDF-TrFE) copolymer thin film prepared at $300^{\circ}C$ showed the optimum piezoelectric properties. At the deposition temperature of $320^{\circ}C$, its piezoelectric coefficient(d33) decreased 25.3 pC/N and piezoelectric voltage coefficient($g_{33}$) $680{\times}10^{-3}V{\cdot}m/N$.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.1
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• pp.16-19
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• 2006

The characteristic of negative differential resistance(NDR) is decreased current when the applied voltage is increased. The NDR is potentially very useful in molecular electronics device schemes. Here, we investigated the NDR characteristic of self-assembled 4,4'-di(ethynylphenyl)-2'-nitro-1-benzenethiolate, which has been well known as a conducting molecule. Self-assembly monolayers(SAMs) were prepared on Au(111), which had been thermally deposited onto $pre-treatment(H_2SO_4:H_2O_2=3:1)$ Si. The Au substrate was exposed to a 1 mM/1 solution of 1-dodecanethiol in ethanol for 24 hours to form a monolayer. After thorough rinsing the sample, it was exposed to a 0.1 ${\mu}M/l$ solution of 4.4'-di(ethynylphenyl)-2'-nitro-1-(thioacetyl)benzene in dimethylformamide(DMF) for 30 min and kept in the dark during immersion to avoid photo-oxidation. After the assembly, the samples were removed from the solutions, rinsed thoroughly with methanol, acetone, and $CH_2Cl_2,$ and finally blown dry with N_2. Under these conditions, we measured electrical properties of self-assembly monolayers(SAMs) using ultra high vacuum scanning tunneling microscopy(UHV-STM). The applied voltages were from -2 V to +2 V with 298 K temperature. The vacuum condition was $6{\time}10^{-8}$ Torr. As a result, we found the NDR voltage of the 4,4'-di(ethynylphenyl)-2'-nitro-1-benzenethiolate were $-1.61{\pm}0.26$ V(negative region) and $1.84{\pm}0.33$ V(positive region). respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.08a
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• pp.41-46
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• 2002

본 논문은 냉, 난방 디지털 온도 조절계(SPC 50)의 Etl의 편차 정 동작에 관한 구현장치 제작과 비례 미.적분기가 At 및 비 At기능에서 설정온도를 $100^{\circ}C$를 유지하는데 기인된 전압전류 및 전력데이터 획득의 요인과 비례미적분 정수 및 노 개선점을 연구하였다. 설정온도를 유지하는 온도변화는 At기능에서 $96.7^{\circ}C\sim102^{\circ}C$ 이며, 비At 기능에서는 $97.6^{\circ}C\sim100.2^{\circ}C$이었다. 온도유지 전압변동은 At기능에서 2V~217V이며, 비 At기능에서 20V~217V 이었다. At와 비 At 기능에서 설정온도 $100^{\circ}C$을 유지하는데 온도를 냉각시키는 환풍기가 온. 오프 되는 시간차는 20초 정도 발생하였다. 온도차 및 전압차는 두 기능간에 비례 미. 적분값 설정이 자동 및 수동이냐에 따라서 차이를 보여주었다. 두 기능에서 설정된 온도값 유지에 따른 전압전류의 승압과 하강의 변동된 변환 데이터는 설정된 온도가 성취되어지는 시간차 및 설정값 유지의 특성을 요인으로 한 PID값과 노의 개선점에 길잡이가 된다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.56-61
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• 2015

Ideal and stretch-out C-V curve were shown at high frequency using SiGe p-FinFET simulation. Average interface trap density can be extracted by the difference of voltage axis on ideal and stretch-out C-V curve. Also, interface trap density(Dit) was extracted by Terman's method that uses the same stretch-out of C-V curve with interface trap characteristic, and average interface trap density was calculated at same energy level. Comparing the average interface trap density, which was found by method using difference of voltage, with Terman's method, it was verified that the two methods almost had the same average interface trap density.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.527-530
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• 2016

This paper presents curvature-compensated reference circuits operating under low-voltage condition and achieving low-power consumption with $0.35-{\mu}m$ standard CMOS process. The proposed circuit can operate under less than 1-V supply voltage by using MOS transistors operating in weak-inversion region. The simulation results shows a low temperature coefficient by using the proposed curvature compensation technique. It generates a graph-shape temperature characteristic that looks like a sine curve, not a bell-shape characteristic presented in other published BGRs without curvature compensation. The proposed circuits operate with 0.9-V supply voltage. First, the voltage reference circuit consumes 176nW power and the temperature coefficient is $26.4ppm/^{\circ}C$. The current reference circuit is designed to operate with 194.3nW power consumption and $13.3ppm/^{\circ}C$ temperature coefficient.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.57-62
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• 1998

In this paper, tunable transconductor shows good linearity over a wide input voltage range are proposed. The proposed transconductor employ operating in the nonsaturation(ie., linear) region to improve circuit simplicity and tunability and 6.8V$\_$p-p/ wide input range. Also the circuit employ source-coupled differential pair to provide true differential input and can achieve both positive and negative transconductance values. The proposed circuits are implemented using a 1.2 $\mu\textrm{m}$ single poly double metal n-well CMOS technology. The THD characteristic of proposed circuit is less than 1% for a differential input voltage of up to 6V$\^$p-p/ when supply bias condition is V$\_$DD/=-V$\_$ss/=5V, I$\_$B/=20, 40${\mu}$A, and frequency of input signal is 1KHz.

• Journal of Advanced Information Technology and Convergence
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• v.8 no.2
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• pp.59-67
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• 2018

The minimum power supply voltage of a typical bandgap current reference (BGCR) is limited by operating temperature and input common mode range (ICMR) of a feedback amplifier. A new BGCR using a bandgap voltage generator (BGVG) is proposed to minimize the effect of temperature, supply voltage, and process variation. The BGVG is designed with proportional to absolute temperature (PTAT) characteristic, and a feedback amplifier is designed with weak-inversion transistors for low voltage operation. It is verified with a $0.18-{\mu}m$ CMOS process with five corners for MOS transistors and three corners for BJTs. The proposed circuit is superior to other reported current references under temperature variation from $-40^{\circ}C$ to $120^{\circ}C$ and power supply variation from 1.2 V to 1.8 V. The total power consumption is $126{\mu}W$ under the conditions that the power supply voltage is 1.2 V, the output current is $10{\mu}A$, and the operating temperature is $20^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Journal of the Korean Vacuum Society
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• v.18 no.3
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• pp.221-228
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• 2009

The purpose of this paper is to discuss the fabrication of $\beta$-PVDF($\beta$-Polyvinylidene fluoride, $\beta$-PVF2) organic thin films through the vapor deposition method and to investigate the ultrasonic response properties of the organic thin films produced. Vapor deposition was performed under the following conditions : the temperature of evaporator, the applied electric field and the pressure of reaction chamber were $270^{\circ}C$, 142.4 kV/cm and $2.0{\times}10^{-5}\;Torr$, respectively. The results showed that the degree of crystallinity increased from 47% to 67.8% with an increase in the substrate temperature. In the case of a sensor response characteristic by varying the distance from 1cm to 100cm, the output voltage decreased from 0.615V to 0.4V.