• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.6
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• pp.531-538
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• 1999

This paper proposes a fuzzy logic controller(FLC) for DC-DC converters in order to obtain good l perfonnances that can not be achieved by linear control tc'Chniques in the presence of wide parameter v variations. 'While the standard controller uses error and derivative of e$\pi$or, the proposed controller uses state v variables. Such method is ve$\pi$ efficient in case of DC-DC converters and can guarantee both stable s small-signal responses and improved large signal responses. The presented approach method is general and c can be applied to any dc-dc converter topologies. Through the simulations of booster, we verify the pro[Xlsed C control tc'Chnique can give a satisfactory perfonnance.

• Journal of IKEEE
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• v.19 no.1
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• pp.110-117
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• 2015

In this paper, a novel trench power MOSFET using a Separate-W-gated technique MOSFET (SWFET) is proposed. Because the SWFET has a very low $Q_{GD}$ compared to other forms of technology, it can be applied to high-speed power systems. The results found that the SWFET-applied $Q_{GD}$ was decreased by 40% when compared to simply using the more conventional trench gate MOSFET. $C_{ISS}$ (input capacitance : $C_{GS}+C_{GD}$), $C_{OSS}$ (output capacitance : $C_{GD}+C_{DS}$) and $C_{RSS}$ (reverse recovery capacitance : $C_{GD}$) were improved by 24%, 40%, and 50%, respectively. The switching characteristics of the inverter circuit shows a 24.9% enhancement of reverse recovery time, and the power efficiency of the DC-DC buck converter increased by 14.2%. In addition, the proposed SWFET does not require additional process steps and There was no degradation in the electrical performance of the current-voltage and on-resistance.

• Journal of Sensor Science and Technology
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• v.13 no.1
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• pp.35-40
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• 2004

A thin-film multijunction thermal converter was fabricated through the process using 6 inch silicon wafer semiconductor process and bulk micromachining. Evanohm R alloy and chromel-constantan were used as a heater and thermocouple materials, respectively. The temperature coefficient of resistance of Evanohm R heater was about 75.12 ppm/$^{\circ}C$ and the voltage sensitivity of the thermal converter indicated about 5.75 mV/mW in air. The transfer differences, measured by FRDC-DC method in the frequency range from 20 Hz to 10 kHz, showed the value under about 1.36 ppm, 0.83 ppm for the film thickness of 500, 200 nm, respectively. And in case of a 200 nm-thick thermal converter, the AC-DC transfer differences seems to be stabilized below the value of 1 ppm in the frequency range from 1 kHz to 500 kHz.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.512-515
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• 2009

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.5
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• pp.664-668
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• 2012

This paper presents the operation strategy of KEPCO(Korea Electric Power COporation) ${\pm}80kV$ 60MW Bipole HVDC system that will be applied between Guemak C/S(converter station) and Hanlim C/S in Jeju island. Unlike intertie HVDC system, this system is located in AC power grid inside. Therefore, the enhancement of system security related with line flow and bus voltages can be major operation strategy. In this paper, in particular, the optimal operation algorithm in the abnormal(not steady state) power system is presented and simulated.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2135-2137
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• 2005

This paper describes the features of electric and magnetic fields produced by lightning discharges. The measuring system consists of fast electric field sensor, crossed-loop magnetic field sensors, signal processing circuit, A/D converter and data acquisition equipment with a 12bit resolution and 10[MS/s] sampling rate. The frequency bandwidth and responsitivity of the electric field measuring system were 40[Hz]${\sim}$2.6 [MHz] and 2.08 (V/m/mV) and those of the magnetic field measuring system were 400[Hz]${\sim}$1[MHz] and 2.78[nT/mV], respectively. The electric and magnetic fields produced by lightning discharges were observed, and the features and parameters of the waveforms were analyzed.

• Journal of Sensor Science and Technology
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• v.7 no.3
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• pp.154-162
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• 1998

A planar Bi-Sb multijunction thermal converter with high thermal sensitivity and small ac-dc transfer error has been fabricated by preparing the bifilar thin film Pt-heater and the hot junctions of thin film Bi-Sb thermopile on the $Si_{3}N_{4}/SiO_{2}/Si_{3}N_{4}$-diaphragm, which functions as a thermal isolation layer, and the cold junctions on the dielectric membrane supported with the Si-substrate, which acts as a heat sink, and its ac-dc transfer characteristics were investigated with the fast reversed dc method. The respective thermal sensitivities of the converter with single bifilar heater were about 10.1 mV/mW and 14.8 mV/mW in the air and vacuum, and those of the converter with dual bifilar heater were about 5.1 mV/mW and 7.6 mV/mW, and about 5.3 mV/mW and 7.8 mV/mW in the air and vacuum for the inputs of inside and outside heaters, indicating that the thermal sensitivities in the vacuum, where there is rarely thermal loss caused by gas, are higher than those in the air. The ac-dc voltage and current transfer difference ranges of the converter with single bifilar heater were about ${\pm}1.80\;ppm$ and ${\pm}0.58\;ppm$, and those of the converter with dual bifilar heater were about ${\pm}0.63\;ppm$ and ${\pm}0.25\;ppm$, and about ${\pm}0.53\;ppm$ and ${\pm}0.27\;ppm$, respectively, for the inputs of inside and outside heaters, in the frequency range below 10 kHz and in the air.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.3
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• pp.204-212
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• 2020

In this study, device suitability analysis is performed by comparing the performance of SiC MOSFET and GaN Transistor, which are WBG power semiconductor devices in the induction heating (IH) system. WBG devices have the advantages of low conduction resistance, switching losses, and fast switching due to their excellent physical properties, which can achieve high output power and efficiency in IH systems. In this study, SiC and GaN are applied to a general half-bridge series resonant converter topology to compare the conduction loss, switching loss, reverse conduction loss, and thermal performance of the device in consideration of device characteristics and circuit conditions. On this basis, device suitability in the IH system is analyzed. A half-bridge series resonant converter prototype using the SiC and GaN of a 650-V rating is constructed to verify device suitability through performance comparison and verified through an experimental comparison of power loss and thermal performance.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.311-313
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• 2008

본 논문에서는 연료전지를 위한 독립형 3kW급 인버터 시스템을 제안한다. 논문에 사용된 연료전지는 26V에서 46V의 가변적인 출력을 가지므로 220V의 교류전압으로 변환하기 위해서 높은 변압비를 가지는 DC/DC 컨버터로에서 400V의 DC링크 전압으로 승압되고 최종적으로 DC/AC 인버터를 통해서 220V의 교류전압으로 변환된다. 또한 DC/DC 컨버터의 직류출력전압을 저장하여 연료전지 초기구동과 제어기 전원에 공급함으로써 독립적인 시스템으로써 동작할 수 있다. 본 논문에서 제안한 시스템은 각 부분별 시뮬레이션을 통해서 검증하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.57-66
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• 1999

This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.